S25FL040A Meet Spansion Inc., S25FL040A Datasheet - Page 23

• Manufacturer Part Number: S25FL040A
• Description: Small Sector For Boot And Parameter Storage 4-megabit Cmos 3.0 Volt Flash Memory With 50 Mhz Spi Bus Interface
• Manufacturer: Meet Spansion Inc.

9.9
July 2, 2007 S25FL040A_00_B2
Page Program (PP)
Note that HPM only protects against changes to the status register. Since BP2:BP0 cannot be changed in
HPM, the size of the protected area of the memory array cannot be changed. Note that HPM provides no
protection to the memory array area outside that specified by BP2:BP0 (Software Protected Mode, or SPM).
If W# is permanently tied high, HPM can never be activated, and only the SPM (BP2:BP0 bits of the Status
Register) can be used.
The Page Program (PP) command changes specified bytes in the memory array (from 1 to 0 only). A WREN
command is required prior to writing the PP command.
The host system must drive CS# low, and then write the PP command, three address bytes, and at least one
data byte on SI. CS# must be driven low for the entire duration of the PP sequence. The command sequence
is shown in
The device programs only the last 256 data bytes sent to the device. If the number of data bytes exceeds this
limit, the bytes sent before the last 256 bytes are discarded, and the device begins programming the last 256
bytes sent at the starting address of the specified page. This may result in data being programmed into
different addresses within the same page than expected. If fewer than 256 data bytes are sent to device, they
are correctly programmed at the requested addresses.
The host system must drive CS# high after the device has latched the 8th bit of the data byte, otherwise the
device does not execute the PP command. The PP operation begins as soon as CS# is driven high. The
device internally controls the timing of the operation, which requires a period of t
be read to check the value of the Write In Progress (WIP) bit while the PP operation is in progress. The WIP
bit is 1 during the PP operation, and is 0 when the operation is completed. The device internally resets the
Write Enable Latch to 0 before the operation completes (the exact timing is not specified).
The device does not execute a Page Program (PP) command that specifies a page that is protected by the
Block Protect bits (BP2:BP0) (see
SCK
CS#
SCK
SI
CS#
SI
Figure 9.9
Mode 3
Mode 0
MSB
40
7
41
6
42
5
Data Byte 2
0
and
43
4
D a t a
1
Table
44
3
Figure 9.9 Page Program (PP) Command Sequence
2
Command
2
45
3
1
9.5.
46
Table 7.1 on page
4
S h e e t
0
47 48 49 50 51 52 53 54 55
5
7
MSB
S25FL040A
6
6
7
5
23 22 21
MSB
8
Data Byte 3
4
9
3
24-Bit Address
10
13).
2
1
3
28
0
2
29
1
30
MSB
0
7
31
MSB
7
6
32
6
5
Data Byte 256
33
5
4
34
Data Byte 1
PP
4
3
35 36 37 38 39
. The Status Register may
3
2
2
1
1
0
0
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