EMD56324P Emlsi Inc., EMD56324P Datasheet - Page 25
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EMD56324P
Manufacturer Part Number
EMD56324P
Description
256m 8m X 32 Mobile Ddr Sdram
Manufacturer
Emlsi Inc.
Datasheet
1.EMD56324P.pdf
(45 pages)
WRITEs
WRITE bursts are initiated with a WRITE command. The starting column and bank addresses are provided with the
WRITE command, and auto precharge is either enabled or disabled for that access. If auto precharge is enabled, the
row being accessed is precharged at the completion of the burst. For the WRITE commands used in the following illus-
trations, auto precharge is disabled. During WRITE bursts, the first valid data-in element will be registered on the first
rising edge of DQS following the WRITE command, and subsequent data elements will be registered on successive
edges of DQS. The LOW state on DQS between the WRITE command and the first rising edge is known as the write
preamble; the LOW state on DQS following the last data-in element is known as the write postamble.
The time between the WRITE command and the first corresponding rising edge of DQS (tDQSS) is specified with a rel-
atively wide range (from 75 percent to 125 percent of one clock cycle). Upon completion of a burst, assuming no other
commands have been initiated, the DQs will remain High-Z and any additional input data will be ignored.
Data for any WRITE burst may be concatenated with or truncated with a subsequent WRITE command. In either case,
a continuous flow of input data can be maintained. The new WRITE command can be issued on any positive edge of
clock following the previous WRITE command. The first data element from the new burst is applied after either the last
element of a completed burst or the last desired data element of a longer burst which is being truncated. The new
WRITE command should be issued x cycles after the first WRITE command, where x equals the number of desired
data element pairs (pairs are required by the 2n-prefetch architecture).
Command
Case 1:
t
Case 2:
t
DQSS
DQSS
Burst Write Operation < Burst Length=4 >
= min
= max
DQ’s
DQ’s
DQS
DQS
CK
CKB
NOP
0
WRITE A
t
t
WPRES
WPRES
t
DQSS
1
t
t
t
WPRE
WPRE
DQSS
NOP
t
DQSH
2
t
DSH
WRITE B
t
t
3
DQSL
DQSH
25
NOP
t
DSS
t
DQSL
t
DSH
NOP
256M: 8M x 32 Mobile DDR SDRAM
t
WPST
NOP
t
DSS
t
WPST
EMD56324P
NOP
Don’t Care
Preliminary
NOP
Rev 0.0