emc646sp16ak Emlsi Inc., emc646sp16ak Datasheet
emc646sp16ak
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emc646sp16ak Summary of contents
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... Tel : +82-64-740-1700 Fax : +82-64-740-1749~1750 / Homepage : www.emlsi.com The attached datasheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your questions about device. If you have any questions, please contact the EMLSI office. EMC646SP16AK 4Mx16 CellularRAM Date Feb. 20 2009 Apr ...
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... Deep Power-down(DPD) mode OPTIONS - Configuration: 64Mb (4 megabit x 16) - Vcc core / VccQ I/O voltage supply: 1.8V - Timing: 70ns access - Frequency: 80 MHz, 104 MHz, 133 MHz - Standby current at 85°C : 140µA(max) - Operating temperature range: Wireless -30°C to +85°C = 7.5ns) CLK 2 EMC646SP16AK 4Mx16 CellularRAM ...
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... Operating Mode (BCR[15]) Default = Asynchronous Operation......................................................................................... 26 Refresh Configuration Register............................................................................................................................................... 27 Partial Array Refresh (RCR[2:0]) Default = Full Array Refresh ......................................................................................... 28 Deep Power-Down (RCR[4]) Default = DPD Disabled ....................................................................................................... 28 Page Mode Operation (RCR[7]) Default = Disabled .......................................................................................................... 28 Device Identification Register.................................................................................................................................................. 28 Electrical Characteristics............................................................................................................................................................. 29 Timing Requirements................................................................................................................................................................... 31 Timing Diagrams.......................................................................................................................................................................... 35 EMC646SP16AK 4Mx16 CellularRAM 3 ...
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... Figure 48: Asynchronous WRITE (ADV# LOW) Followed by Burst READ ............................................................................. 59 Figure 49: Burst READ Followed by Asynchronous WRITE (WE# - Controlled) ..................................................................... 60 Figure 50: Burst READ Followed by Asynchronous WRITE Using ADV# ............................................................................... 51 Figure 51: Asynchronous WRITE Followed by Asynchronous READ - ADV# LOW ............................................................... 62 Figure 52: Asynchronous WRITE Followed by Asynchronous READ ..................................................................................... 63 EMC646SP16AK 4Mx16 CellularRAM 4 45 ...
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... Deep Power-Down Specifications ............................................................................................................................... 30 Table 12: Partial-Array Specifications and Conditions ................................................................................................................ 30 Table 13: Capacitance ................................................................................................................................................................ 30 Table 14: Asynchronous READ Cycle Timing Requirements ...................................................................................................... 31 Table 15: Burst READ Cycle Timing Requirements .................................................................................................................... 32 Table 16: Asynchronous WRITE Cycle Timing Requirements .................................................................................................... 33 Table 17: Burst WRITE Cycle Timing Requirements ................................................................................................................... 34 Table 18: Initialization and DPD Timing Parameters ................................................................................................................... 35 EMC646SP16AK 4Mx16 CellularRAM 5 ...
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... Note: Functional block diagrams illustrate simplified device operation. See pin descriptions(Table 1); Bus operations table(Table 2); and timing diagrams for detailed information. Address Decode 4,096K x 16 Logic DRAM MEMORY ARRAY Refresh Configuration Register (RCR) Device ID Register (DIDR) Bus Configuration Register (BCR) Internal 6 EMC646SP16AK 4Mx16 CellularRAM Input Output DQ[7:0] MUX and DQ[15:8] Buffers External ...
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... Vss must be connected to ground. VssQ Supply VssQ must be connected to ground. Note: 1. When using asynchronous mode or page mode exclusively, CLK and ADV# inputs can be tied to Vss. WAIT will be asserted but should be ignored during asynchronous and page mode operations. EMC646SP16AK Descriptions 7 4Mx16 CellularRAM ...
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... EMC646SP16AK 4Mx16 CellularRAM UB WAIT DQ[15:0] LB Low-z Data out L L Low-z Data High-z High Low Low-z High-z Config Low-z Reg.out X ...
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... When they reach a stable level at or above 1.7V, the device will require 150µs to complete its self-initialization process. During the initialization period, CE# should remain HIGH. When initialization is complete, the device is ready for normal operation. Figure 2: Power-Up Initialization Timing Vcc=1.7V Vcc VccQ t ≥ 150µs PU Device ready for normal operation Device Initialization 9 EMC646SP16AK 4Mx16 CellularRAM ...
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... During asychronous operation, the CLK input must be held static LOW. WAIT will be driven while the device is enabled and its state should be ignored. WE# LOW time must be limited to t Figure 3: READ Operation (ADV# LOW) WE# Address DATA LB#/UB# Note: ADV# must remain Low for PAGE MODE operation. CEM CE# OE# Address Valid Data Valid t = READ Cycle Time RC 10 EMC646SP16AK 4Mx16 CellularRAM Don’t Care ...
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... Figure 5: Page Mode READ Operation (ADV# LOW) CE# OE# WE# Address DATA LB#/UB# CE# OE# < t CEM Address Valid Data Valid t = WRITE Cycle Time WC . CEM t ＜ CEM Add0 Add1 Add2 Add3 APA APA EMC646SP16AK 4Mx16 CellularRAM Don’t Care APA D3 Don’t Care ...
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... Note: Non-default BCR settings for burst mode READ (4-word burst): Fixed or variable latency; Latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay. Diagram in the figure 6 is representative of variable latency with no refresh collision or fixed-latency access. Latency Code 2 (3 clocks EMC646SP16AK 4Mx16 CellularRAM Don’ ...
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... WAIT output will continue to be active, and as a result no other devices should directly share the WAIT connection to the controller. To continue the burst sequence, OE# is taken LOW, then CLK is restarted after valid data is available on the bus. The CE# LOW time Latency Code 2(3 clocks EMC646SP16AK 4Mx16 CellularRAM ...
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... Additional WAIT states inserted to allow refresh completion Note: Non-default BCR settings for refresh collision during variable-latency READ operation: Latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay. EMC646SP16AK . If a burst suspension will cause CE# to remain LOW for CEM Don’ ...
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... When both the LB# and UB# are disabled (HIGH) during an operation, the device will disable the data bus from receiving or transmitting data. Although the device will seem to be deselected, it remains in an active mode as long as CE# remains LOW. External CellularRAM Pull-Up/ Pull-Down Resistor WAIT WAIT WAIT Other Other Device Device 15 EMC646SP16AK 4Mx16 CellularRAM . Mixed-mode operation facilitates a CEM ...
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... During this 150µs period, the current consumption will be higher than the specified standby levels, but considerably lower than the active current specification. DPD can be enabled by writing to the RCR using CRE or the software access sequence; DPD starts when CE# goes HIGH. DPD is disabled the next time CE# goes LOW and stays LOW for at least 10µs. EMC646SP16AK 16 4Mx16 CellularRAM ...
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... Select control register 1 A[19:18] CRE ADV# CE# OE# WE# LB#/UB# DQ[15:0] Note: 1. A[19:18] = 00b to load RCR, and 10b to load BCR. t AVH t AVS t AVH t VP Initiate control register access Write address bus value to control register 17 EMC646SP16AK 4Mx16 CellularRAM Address Address t CPH Data Valid Don’t Care ...
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... A[19:18] = 00b to load RCR, and 10b to load BCR. 3. CE# must remain LOW to complete a burst-of-one WRITE. WAIT must be monitored; additional WAIT cycles caused by refresh collisions require a corresponding number of additional CE# LOW cycles. Address Latch control register address Address t CBPH Note 3 High-Z 18 EMC646SP16AK 4Mx16 CellularRAM Data Valid Don’t Care ...
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... Note: A[19:18] = 00b to read RCR, 10b to read BCR, and 01b to read DIDR. t AVH AVH t AVS AADV Initiate register access OLZ Valid 19 EMC646SP16AK 4Mx16 CellularRAM Address Address t CPH OHZ t BHZ Data Valid Undefined Don’t Care ...
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... CE# must remain LOW to complete a burst-of-one READ. WAIT must be monitored; additional WAIT cycles caused by refresh collisions require a corresponding number of additional CE# LOW cycles. Latch control register address t t CBPH ABA Note OHZ BOE t ACLK t OLZ High-Z t KOH CR Valid 20 EMC646SP16AK 4Mx16 CellularRAM Address Address Data Valid Undefined Don’t Care ...
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... WRITE WRITE ADDRESS ADDRESS ADDRESS Max Max XXXXh CR Value In RCR : 0000h BCR : 0001h READ WRITE READ ADDRESS ADDRESS ADDRESS Max Max XXXXh CR Value Iout RCR : 0000h BCR : 0001h DIDR : 0002h 21 EMC646SP16AK 4Mx16 CellularRAM Max Don’t Care Max Don’t Care ...
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... Code 1 - Reserved 0 Code 2 1 Code 3 (default) 0 Code 4 1 Code 5 0 Code 6 1 Code 7 - Reserved BCR[10] WAIT Polarity 0 Active LOW 1 Active HIGH (default) 22 EMC646SP16AK 4Mx16 CellularRAM WAIT Drive Burst Reserved Reserved Strength Wrap(BW)* Must be set to “0” ...
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... EMC646SP16AK 4Mx16 CellularRAM 32 Word Continuous Burst Length Burst Linear Linear 0-1-2 ... 29-30-31 0-1-2-3-4-5-6-... 1-2-3 ... 30-31-0 1-2-3-4-5-6-7-... 2-3-4 ... 31-0-1 2-3-4-5-6-7-8-... 3-4-5 ... 0-1-2 3-4-5-6-7-8-9-... 4-5-6 ... 1-2-3 4-5-6-7-8-9-10-... 5-6-7 ... 2-3-4 5-6-7-8-9-10-11-... 6-7-8 ... 3-4-5 6-7-8-9-10-11-12-... 7-8-9 ... 4-5-6 7-8-9-10-11-12-13-... ... ... 14-15-16-...-11-12-13 14-15-16-17-18-19-20-... 15-16-17...-12-13-14 15-16-17-18-19-20-21-... ... ... 30-31-0-...-27-28-29 30-31-32-33-34-... 31-0-1-... -28-29-30 31-32-33-34-35- ...
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... Note: Non-default BCR setting: WAIT active LOW. Impedance Typ (Ω ) Full 25~30 1/2 50 (default) 1/4 100 Reserved End of row 24 EMC646SP16AK 4Mx16 CellularRAM Use Recommendation CL = 30pF to 50pF CL = 15pF to 30pF 104 MHz at light load CL = 15pF or lower BCR[ Data valid in current cycle BCR[ Data valid in next cycle Don’t Care ...
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... OL 1 Latency Normal Refresh Collision Valid Valid Output Output (default) Valid Output 25 EMC646SP16AK 4Mx16 CellularRAM Max Input CLK Frequency (MHz) 133 104 66(15ns) 66(15ns) 52(19.2ns) 104(9.62ns) 104(9.62ns) 80(12.5ns) 133(7.5ns Valid Valid Valid Output Output Output ...
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... Cycles AADV ACLK Valid Valid Output Output Valid Valid Input Input 26 EMC646SP16AK 4Mx16 CellularRAM Max Input CLK Frequency (MHz) 104 33(30ns) 33(30ns) 52(19.2ns) 52(19.2ns) 66(15ns) 66(15ns) 75(13.3ns) 75(13.3ns) 104(9.62ns) 80(12.5ns Valid Valid Valid Output Output Output ...
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... Page Mode Enable DPD Page Reserved Setting is ignored (Default 00b) RCR[4] Deep Power-Down 0 DPD Enable 1 DPD Disable (default) 27 EMC646SP16AK 4Mx16 CellularRAM Reserved PAR Must be set to “0” RCR[2] RCR[1] RCR[0] Refresh Coverage Full array (default ...
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... One-eighth of die 380000h-3FFFFFh DIDR[14:11] DIDR[10:8] Device version Device density Bit Version Density Setting Setting 2nd 0001b 64Mb 28 EMC646SP16AK 4Mx16 CellularRAM Size 4 Meg Meg Meg x 16 512 Meg Meg Meg x 16 512 DIDR[7:5] CellularRAM generation Bit ...
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... Symbol OUT 0V, CE CCQ CCQ SB 29 EMC646SP16AK 4Mx16 CellularRAM Rating -0.30V to VccQ + 0.3V -0.2V to +2.45V -0.2V to +2.45V -55°C to +150°C -30°C to +85°C +260°C Min Max 1.7 1.95 1.7 1.95 VccQ - 0.4 VccQ + 0.2 -0.20 0.4 0.80 VccQ 0.20 VccQ 1 1 Typ Max 70ns ...
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... Note: All tests are performed with the outputs configured for default setting of half drive strength (BCR[5:4] = 01b). Conditions V = VccQ or 0V; IN =25°C and not guaranteed. A Conditions IPAR Conditions VccQ/2 Test Points Test Points 50-Ohm DUT 30pF 30 EMC646SP16AK 4Mx16 CellularRAM Symbol Typ Symbol Array Partition Full 1/2 Standard power (no 1/4 designation ) 1/8 0 Symbol Min Max C 2.0 ...
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... CVS OHZ t 3 OLZ toward VccQ/ EMC646SP16AK 4Mx16 CellularRAM Unit Note Max µ ...
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... 1.2 KHKL t - 5.5 KHTL t 2 KOH OHZ t 3 OLZ refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# CEM or V toward VccQ/ EMC646SP16AK 4Mx16 CellularRAM 104MHz 80MHZ Min Max Min Max 35 ...
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... WHZ WPH toward VccQ/ EMC646SP16AK 4Mx16 CellularRAM 70ns Unit Note Max - 7 ...
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... CEM t 1 CEW t 7.5 CLK t 2.5 CSP t 1 KHKL t - KHTL refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# CEM or V toward VccQ/ EMC646SP16AK 4Mx16 CellularRAM 104MHz 80MHZ Max Min Max Min - 7 9. ...
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... Table 18: Initialization and DPD Timing Parameters Symbol t DPD t DPDX 1. DPD DPDX DPD Enabled DPD EXIT Min Max 150 10 150 35 EMC646SP16AK 4Mx16 CellularRAM (MIN) Vcc Device ready for normal operation t PU Device ready for Device Initialization normal operation Unit µ s µ s µ s ...
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... IH CE LB#/ DQ[15:0] High WAIT High Valid Address OLZ t BLZ t LZ Valid Output t CEW 36 EMC646SP16AK 4Mx16 CellularRAM BHZ t OHZ t HZ High-Z Don’t Care Undefined ...
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... OE WE High-Z DQ[15: High-Z WAIT V OL Valid Address AVS AVH t AADV CVS OLZ t BLZ t LZ Valid Output t CEW 37 EMC646SP16AK 4Mx16 CellularRAM BHZ t OHZ t HZ High-Z Don’t Care Undefined ...
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... Valid Valid Address Address CEM OLZ t t APA BLZ Valid Valid Output Output t CEW 38 EMC646SP16AK 4Mx16 CellularRAM Valid Valid Address Address BHZ t OHZ Valid Valid Output Output t HZ High-Z Don’t Care Undefined ...
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... KHKL Valid Address CEM t t ABA CSP t BOE OLZ KHTL CEW t ACLK High-Z Valid Output READ Burst Identified (WE# = HIGH) 39 EMC646SP16AK 4Mx16 CellularRAM OHZ t HD High-Z t KOH High-Z Don’t Care Undefined ...
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... CEM t t CSP ABA t BOE OLZ KHTL t CEW t ACLK Valid Output READ Burst Identified (WE# = HIGH) 40 EMC646SP16AK 4Mx16 CellularRAM CBPH OHZ t HD High-Z t KOH Valid Valid Valid Output Output Output Don’t Care Undefined High-Z ...
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... Valid Address t AVH AADV t CEM t CSP CEW READ Burst Identified (WE# = HIGH) 41 EMC646SP16AK 4Mx16 CellularRAM KHKL OHZ t BOE t OLZ KHTL High ACLK KOH High-Z Valid Output Don’t Care Undefined ...
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... AADV t CSP t CEM BOE t OLZ KHTL t CEW t ACLK Valid Output READ Burst Identified (WE# = HIGH) 42 EMC646SP16AK 4Mx16 CellularRAM KHKL CBPH OHZ KOH Valid Valid Valid Output Output Output Don’t Care Undefined High-Z ...
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... OE# can stay LOW during burst suspend. If OE# is LOW, DQ[15:0] will continue to output valid data. t CLK CEM HD t BOE t OLZ t KOH Valid Valid Valid Output Output Output t ACLK 43 EMC646SP16AK 4Mx16 CellularRAM Note 2 t CBPH OHZ OHZ Note High-Z t BOE t OLZ Valid Valid Valid Output Output Output Don’ ...
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... For burst READs, CE# must go HIGH before the second CLK after the WAIT period begins ( before the second CLK after WAIT asserts with BCR[8]=0, or before the third CLK after WAIT asserts with BCR[8]= CLK CSP Note 2 End of row Valid Valid Output Output KHTL t KOH 44 EMC646SP16AK 4Mx16 CellularRAM High-Z Don’t Care Undefined ...
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... Non-default BCR settings for burst READ at end of row : fixed or variable latency, WAIT active LOW, WAIT asserted during delay. (shown as solid line) 2. WAIT will be assert for LC cycles for variables latency cycles for fixed latency. End of row Valid output t KTHL Note 2 t KOH 45 EMC646SP16AK 4Mx16 CellularRAM Valid output Valid output t KTHL t KOH Don’t Care ...
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... OE WE DQ[15:0] IH High DQ[15:0] OH OUT WAIT High Valid Address WPH WP t WHZ CEW 46 EMC646SP16AK 4Mx16 CellularRAM CPH Valid Input t HZ High-Z Don’t Care ...
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... DQ[15: High DQ[15: OUT WAIT High Valid Address WPH WP t WHZ CEW 47 EMC646SP16AK 4Mx16 CellularRAM Valid Input t HZ High-Z Don’t Care ...
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... WPH DQ[15: High DQ[15: OUT WAIT High Valid Address WHZ t CEW 48 EMC646SP16AK 4Mx16 CellularRAM Valid Input High-Z Don’t Care ...
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... V IL DQ[15: High DQ[15: OUT WAIT High Valid Address t t AVS AVH CVS WHZ t CEW 49 EMC646SP16AK 4Mx16 CellularRAM t WPH Valid Input High-Z Don’t Care ...
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... WAIT asserts for LC cycles for both fixed and variable latency Latency Code (BCR[13:11]). 3. t required if t > 20ns. AS CSP t CLK Valid Address CSP t CEM KHTL CEW Note (WE# = Low) 50 EMC646SP16AK 4Mx16 CellularRAM KHKL CBPH t HZ High-Z Don’t Care ...
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... AS CSP t CLK t SP Valid Address t AVH CSP t CEM KHTL CEW Note WRITE Burst Identified (WE# = Low) 51 EMC646SP16AK 4Mx16 CellularRAM KHKL CBPH t HZ High-Z Don’t Care ...
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... For burst WRITEs, CE# must go HIGH before the second CLK after the WAIT period begins(before the second CLK after WAIT asserts with BCR[8]=0, or before the third CLK after WAIT asserts with BCR[8]=1). t CLK CSP Note Valid Valid Input Input End of row t KOH t KHTL 52 EMC646SP16AK 4Mx16 CellularRAM High-Z Don’t Care ...
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... Non-default BCR settings for burst WRITE at end of row : Fixed or variable latency, WAIT active LOW, WAIT asserted during delay. (shown as solid line) 2. WAIT will be assert for LC cycles for variables latency cycles for fixed latency. End of row t HD Valid input Valid input t KTHL t KOH Note 2 53 EMC646SP16AK 4Mx16 CellularRAM Valid input Valid input t KTHL t KOH Don’t Care ...
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... See burst interrupt diagrams for cases where CE# stays LOW between bursts. CEM t CLK CBPH Note refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# CEM 54 EMC646SP16AK 4Mx16 CellularRAM Valid Address CSP BOE t t ACLK KOH ...
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... ACLK Valid High-Z Output V OE# IH 2nd Cycle Write LB#/UB# IH 2nd Cycle Write DQ[15:0] IN High-Z 2nd Cycle Write V IL CEM 55 EMC646SP16AK 4Mx16 CellularRAM t HD High-Z t OHZ t KOH Valid Valid Valid Valid Output Output Output Output t ACLK Don’ ...
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... BOE ACLK High EMC646SP16AK 4Mx16 CellularRAM t HD High OHZ KOH Valid Valid Valid Valid Output Output Output Output Don’t Care . CEM Undefined ...
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... ACLK High EMC646SP16AK 4Mx16 CellularRAM OHZ t BOE KOH Valid Valid Valid Valid Output Output Output Output Don’t Care . CEM High-Z ...
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... Valid Address t t AVH CBPH Note WPH Data . A refresh opportunity is satisfied by either of the following two CEM 58 EMC646SP16AK 4Mx16 CellularRAM t CLK Valid Address CSP BOE CEW t t ...
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... CE# HIGH CE# HIGH for longer than 15ns Valid Address CBPH Note WPH Data . A refresh opportunity is satisfied by either of the following two CEM 59 EMC646SP16AK 4Mx16 CellularRAM t CLK Valid Address CSP BOE CEW ...
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... A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# HIGH CE# HIGH for longer than 15ns. t CLK BOE OLZ KHTL CEW t t ACLK Valid Output 60 EMC646SP16AK 4Mx16 CellularRAM t WC Valid Address CBPH CW t Note OHZ CEW High-Z KOH Don’ ...
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... CE# HIGH CE# HIGH for longer than 15ns. t CLK BOE OLZ KHTL CEW t ACLK Valid Output 61 EMC646SP16AK 4Mx16 CellularRAM Valid Address t t AVS AVH CBPH Note OHZ ...
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... CE#-controlled WRITEs. CPH Valid Address CPH Note WPH High-Z Data 62 EMC646SP16AK 4Mx16 CellularRAM Valid Address BLZ t OLZ V OH Valid Output V OL Don’t Care ) to schedule the appropriate refresh CPH OHZ ...
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... AVH CPH t CW Note WPH Data Data 63 EMC646SP16AK 4Mx16 CellularRAM Valid Address OLZ t BLZ V OH Valid Output High Don’t Care ) to schedule the appropriate refresh CPH OHZ t ...
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... U ----------------------- 3.0V S ----------------------- 2.5V R ----------------------- 2.0V P ----------------------- 1.8V L ----------------------- 1.5V 7. Organization 8 ---------------------- x8 bit 16 ---------------------- x16 bit 32 ---------------------- x32 bit EMC646SP16AK 4Mx16 CellularRAM 7. Organization 8. Version Blank ----------------- Mother die A ----------------------- 2’nd generation B ----------------------- 3’rd generation C ----------------------- 4’th generation D ----------------------- 5’th generation 9. Option Blank ---- No optional mode J ------------ Non-RBC ...