emc646sp16ak Emlsi Inc., emc646sp16ak Datasheet - Page 4

• Manufacturer Part Number: emc646sp16ak
• Description: 4mx16 Bit Cellularram
• Manufacturer: Emlsi Inc.

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Functional Block Diagram - 4 meg x 16 ................................................................................................................. 6
Power-Up Initialization Timing ............................................................................................................................... 9
READ Operation (ADV# LOW) .............................................................................................................................. 10
WRITE Operation (ADV# LOW) ............................................................................................................................. 11
Page Mode READ Operation (ADV# LOW) ........................................................................................................... 11
Burst Mode READ (4-word burst)........................................................................................................................... 12
Burst Mode WRITE (4-word burst).......................................................................................................................... 13
Refresh Collision During Variable-Latency READ Operation ................................................................................. 14
Wired or WAIT Configuration ................................................................................................................................. 15
Configuration Register WRITE, Asynchronous Mode, Followed by READ ARRAY Operation .............................. 17
Configuration Register WRITE, Synchronous Mode, Followed by READ ARRAY Operation ................................ 18
Register READ, Asynchronous Mode, Followed by READ ARRAY Operation ...................................................... 19
Register READ, Synchronous Mode, Followed by READ ARRAY Operation ........................................................ 20
Load Configuration Register .................................................................................................................................. 21
Read Configuration Register ................................................................................................................................. 21
Bus Configuration Register Definition .................................................................................................................... 22
WAIT Configuration During Burst Operation .......................................................................................................... 24
Latency Counter (Variable Initial Latency, No Refresh Collision) ........................................................................... 25
Latency Counter (Fixed Latency) ........................................................................................................................... 26
Refresh Configuration Register Mapping ............................................................................................................... 27
AC Input/Output Reference Waveform .................................................................................................................. 30
AC Output Load Circuit .......................................................................................................................................... 30
Initialization Period ................................................................................................................................................. 35
DPD Entry and Exit Timing Parameters ................................................................................................................. 35
Asynchronous READ ............................................................................................................................................. 36
Asynchronous READ Using ADV# ......................................................................................................................... 37
PAGE MODE READ .............................................................................................................................................. 38
Single-Access Burst READ Operation - Variable Latency ..................................................................................... 39
4-Word Burst READ Operation - Variable Latency ................................................................................................ 40
Single-Access Burst READ Operation - Fixed Latency .......................................................................................... 41
4-Word Burst READ Operation - Fixed Latency ..................................................................................................... 42
READ Burst Suspend ............................................................................................................................................ 43
Burst READ at End-of-Row (Wrap off) ................................................................................................................... 44
Burst READ Row Boundary Crossing ................................................................................................................
CE# - Controlled Asychronous WRITE .................................................................................................................. 46
LB#/UB# - Controlled Asychronous WRITE ........................................................................................................... 47
WE# - Controlled Asychronous WRITE ................................................................................................................. 48
Asynchronous WRITE Using ADV# ....................................................................................................................... 49
Burst WRITE Operation - Variable Latency Mode ................................................................................................. 50
Burst WRITE Operation - Fixed Latency Mode ...................................................................................................... 51
Burst WRITE at End-of-Row (Wrap off) ................................................................................................................. 52
Burst WRITE Row Boundary Crossing ................................................................................................................ 53
Burst WRITE Followed by Burst READ ................................................................................................................ 54
Burst READ Interrupted by Burst READ or WRITE................................................................................................ 55
Burst WRITE Interrupted by Burst WRITE or READ - Variable Latency Mode ...................................................... 56
Burst WRITE Interrupted by Burst WRITE or READ - Fixed Latency Mode ........................................................... 57
Asynchronous WRITE Followed by Burst READ ................................................................................................... 58
Asynchronous WRITE (ADV# LOW) Followed by Burst READ ............................................................................. 59
Burst READ Followed by Asynchronous WRITE (WE# - Controlled) ..................................................................... 60
Burst READ Followed by Asynchronous WRITE Using ADV# ............................................................................... 51
Asynchronous WRITE Followed by Asynchronous READ - ADV# LOW ............................................................... 62
Asynchronous WRITE Followed by Asynchronous READ ..................................................................................... 63
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EMC646SP16AK
4Mx16 CellularRAM
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