emc163sp16k Emlsi Inc., emc163sp16k Datasheet
emc163sp16k
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emc163sp16k Summary of contents
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... Tel : +82-64-740-1700 Fax : +82-64-740-1749~1750 / Homepage : www.emlsi.com The attached datasheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your questions about device. If you have any questions, please contact the EMLSI office. EMC163SP16K 1Mx16 CellularRAM AD-MUX Draft Date Apr ...
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... On-chip temperature compensated self refresh (TCSR) Partial array refresh (PAR) OPTIONS - Configuration: 16Mb (1 megabit x 16) - Vcc core / VccQ I/O voltage supply: 1.8V - Timing: 70ns access - Frequency: 83 MHz, 104 MHz, 133 MHz - Standby current at 85°C : 70µA(max) - Operating temperature range: Wireless -30°C to +85°C EMC163SP16K 1Mx16 CellularRAM AD-MUX 2 ...
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... Drive Strength (BCR[5:4]) Default = Outputs Use Half-Drive Strength .......................................................................... 25 WAIT Polarity (BCR[10]) Default = WAIT Active HIGH................................................................................................... 26 Initial Access Latency (BCR[14]) Default = Variable....................................................................................................... 26 Operating Mode (BCR[15]) Default = Asynchronous Operation..................................................................................... 28 Refresh Configuration Register........................................................................................................................................... 28 Device Identification Register.............................................................................................................................................. 29 Electrical Characteristics......................................................................................................................................................... 30 Timing Requirements.............................................................................................................................................................. 32 Timing Diagrams..................................................................................................................................................................... 36 EMC163SP16K 1Mx16 CellularRAM AD-MUX 3 ...
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... Figure 33: Burst WRITE Terminate at End-of-Row (Wrap off) ........................................................................... 46 Figure 34: Burst WRITE Row Boundary Crossing ............................................................................................ 47 Figure 35: Burst WRITE Followed by Burst READ ............................................................................................ 48 Figure 36: Asynchronous WRITE Followed by Burst READ .............................................................................. 49 Figure 37: Burst READ Followed by Asynchronous WRITE .............................................................................. 50 Figure 38: Asynchronous WRITE Followed by Asynchronous READ ............................................................... 51 EMC163SP16K 1Mx16 CellularRAM AD-MUX 4 6 ...
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... Table 10: Electrical Characteristics and Operating Conditions ......................................................................................... 30 Table 11: Partial-Array Refresh Specifications and Conditions.......................................................................................... 31 Table 12: Capacitance ...................................................................................................................................................... 31 Table 13: Asynchronous READ Cycle Timing Requirements ............................................................................................ 32 Table 14: Burst READ Cycle Timing Requirements ......................................................................................................... 33 Table 15: Asynchronous WRITE Cycle Timing Requirements .......................................................................................... 34 Table 16: Burst WRITE Cycle Timing Requirements ........................................................................................................ 35 Table 17: Initialization Timing Parameters ........................................................................................................................ 36 EMC163SP16K 1Mx16 CellularRAM AD-MUX 5 ...
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... Note: Functional block diagrams illustrate simplified device operation. See pin descriptions; Bus operations table; and timing diagrams for detailed information. Address Decode 1,024K x 16 Logic DRAM MEMORY ARRAY Refresh Configuration Register (RCR) Device ID Register (DIDR) Bus Configuration Register (BCR) Internal 6 EMC163SP16K 1Mx16 CellularRAM AD-MUX Input Output A/DQ[7:0] MUX and A/DQ[15:8] Buffers External ...
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... I/O power supply: (1.70V.1.95V) Power supply for input/output buffers. VSS Supply VSS must be connected to ground. VSSQ Supply VSSQ must be connected to ground. Note: 1. When using asynchronous mode exclusively, CLK can be tied to VSSQ or VCCQ. WAIT should be ignored during asynchronous mode operations. EMC163SP16K 1Mx16 CellularRAM AD-MUX Descriptions 7 ...
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... EMC163SP16K 1Mx16 CellularRAM AD-MUX UB#/ WAIT A/DQ[15: Low-z Data out L L High-z Data High-z High Low Low-z High-z Config Low-z Reg ...
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... Until the end of VccQ and remain HIGH. When initialization is complete, the device is ready for normal operation. Figure 2: Power-Up Initialization Timing Vcc VccQ Vcc=1. Device Initialization 9 EMC163SP16K 1Mx16 CellularRAM AD-MUX t PU, CE# should track Device ready for normal operation ...
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... A/DQ bus. The data to be written is latched on the rising edge of CE#, WE#, UB#, or LB# (whichever occurs first). Dur- ing asynchronous operations with burst mode enabled, the CLK input must be held static(HIGH or LOW). WAIT will be driven during asynchronous READs, and its state should be ignored. WE# LOW time must be limited to tCEM. EMC163SP16K 1Mx16 CellularRAM AD-MUX 10 ...
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... Figure 3: READ Operation A/DQ[15:0] Figure 4: WRITE Operation A/DQ[15:0] Valid A[19:16] Address CE# OE# WE# Valid High-Z Address ADV# LB#/UB# Valid A[19:16] Address CE# OE# t CEM WE# Valid Address ADV# LB#/UB# Don’t Care 11 EMC163SP16K 1Mx16 CellularRAM AD-MUX Valid Data Don’t Care Valid Data Undefined ...
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... Non-default BCR settings for burst mode READ (4-word burst): Fixed or variable latency; Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. Diagram in the figure above is representative of variable latency with no refresh collision or fixed-latency access READ Burst Identified 12 EMC163SP16K 1Mx16 CellularRAM AD-MUX Address Address (WE# = HIGH) Don’t Care Undefined ...
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... The CE# LOW time is limited by refresh considerations. CE# must not stay LOW longer than t to remain LOW for longer than t , CE# should be taken HIGH and the burst restarted with a new CE# LOW/ADV# LOW cycle. CEM WRITE Burst Identified 13 EMC163SP16K 1Mx16 CellularRAM AD-MUX Address Address (WE# = LOW) Don’t Care . If a burst suspension will cause CE# CEM ...
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... Additional WAIT states inserted to allow refresh completion. Note: Non-default BCR settings for refresh collision during variable-latency READ operation: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay EMC163SP16K 1Mx16 CellularRAM AD-MUX D3 D2 Don’t Care Undefined ...
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... LB# and UB# are disabled (HIGH) during an operation, the device will disable the data bus from receiving or transmitting data. Although the device will seem to be deselected, it remains in an active mode as long as CE# remains LOW. External CellularRAM Pull-Up Pull-Down Resistor WAIT WAIT WAIT Other Other Device Device 15 EMC163SP16K 1Mx16 CellularRAM AD-MUX . Mixed-mode operation CEM ...
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... Table 7). READ and WRITE operations to address ranges receiving refresh will not be affected. Data stored in addresses not receiving refresh will become corrupted. When re-enabling additional portions of the array, the new portions are available immediately upon writing to the RCR. EMC163SP16K 1Mx16 CellularRAM AD-MUX 16 ...
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... OE# WE# LB#/UB# OPCODE A/DQ[15:0] Note: A[19:18] = 00b to load RCR, and 10b to load BCR AVS AVH t AVS t AVH t VP Initiate Control register access Write address bus value to control register 17 EMC163SP16K 1Mx16 CellularRAM AD-MUX Address Address t CPH Valid Address data Don’t Care ...
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... CE# must remain LOW to complete a burst-of-one WRITE. WAIT must be monitored; additional WAIT cycles caused by refresh collisions require a corresponding number of additional CE# LOW cycles. Address Latch control register address Address t CBPH Note3 Address High-Z 18 EMC163SP16K 1Mx16 CellularRAM AD-MUX Valid data Don’t Care ...
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... Note: A[19:18] = 00b to read RCR, 10b to read BCR, and 01b to read DIDR. t AVH AVS t t AVH AA t AVS AADV Initiate register access OLZ Valid CR 19 EMC163SP16K 1Mx16 CellularRAM AD-MUX Address Address t CPH OHZ t BHZ Valid Address data Undefined Don’t Care ...
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... CE# must remain LOW to complete a burst-of-one READ. WAIT must be monitored; additional WAIT cycles caused by refresh collisions require a corresponding number of additional CE# LOW cycles. Latch control register address HD t ABA Note3 OHZ BOE KOH ACLK OLZ Valid CR 20 EMC163SP16K 1Mx16 CellularRAM AD-MUX Address Address t CBPH Address High-Z Undefined Don’t Care Valid data ...
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... The use of the software sequence does not affect the ability to perform the standard (CRE-controlled) method of loading the configuration registers. However, the software nature of this access mechanism eliminates the need for CRE. If the software mechanism is used, CRE can simply be tied to VSS. The port line often used for CRE control purposes is no longer required. EMC163SP16K 1Mx16 CellularRAM AD-MUX 21 ...
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... XXXX XXXX (MAX) (MAX) READ READ Address Address (MAX) (MAX) Address Address XXXX XXXX (MAX) (MAX) 22 EMC163SP16K 1Mx16 CellularRAM AD-MUX WRITE WRITE Address (MAX) 0ns (min); Note 1 Address CR Value (MAX) in RCR : 0000h Don’t Care BCR : 0001h WRITE READ Address (MAX) 0ns (min) ...
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... Code 8 1 Code 1 - Reserved 0 Code 2 1 Code 3 (default) 0 Code 4 1 Code 5 0 Code 6 1 Code 7 - Reserved BCR[10] WAIT Polarity 0 Active LOW 1 Active HIGH (default) 23 EMC163SP16K 1Mx16 CellularRAM AD-MUX A/DQ A/DQ A/DQ A/ [5: Drive Burst Reserved Reserved Strength Wrap(BW) Must be set to “0” Must be set to “0” ...
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... EMC163SP16K 1Mx16 CellularRAM AD-MUX 32 Word Continuous Burst Length Burst Linear Linear 0-1-2 ... 29-30-31 0-1-2-3-4-5-6-... 1-2-3 ... 30-31-0 1-2-3-4-5-6-7-... 2-3-4 ... 31-0-1 2-3-4-5-6-7-8-... 3-4-5 ... 0-1-2 3-4-5-6-7-8-9-... 4-5-6 ... 1-2-3 4-5-6-7-8-9-10-... 5-6-7 ... 2-3-4 5-6-7-8-9-10-11-... 6-7-8 ... 3-4-5 6-7-8-9-10-11-12-... 7-8-9 ... 4-5-6 7-8-9-10-11-12-13-... ... ... 14-15-16-...-11-12-13 14-15-16-17-18-19-20-... 15-16-17...-12-13-14 15-16-17-18-19-20-21-... ... ... 30-31-0-...-27-28-29 30-31-32-33-34-... 31-0-1-... -28-29-30 31-32-33-34-35- ...
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... See Table 4 for additional information. Table 4: Drive Strength BCR[5] BCR[4] Drive Strength Impedance Typ (Ω ) Full 25~30 1/2 50 (default) 1/4 100 Reserved 25 EMC163SP16K 1Mx16 CellularRAM AD-MUX Use Recommendation CL = 30pF to 50pF CL = 15pF to 30pF 104 MHz at light load CL = 15pF or lower ...
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... D1 D2 Latency 1 Normal Refresh Collision EMC163SP16K 1Mx16 CellularRAM AD-MUX BCR[ Data Valid in current cycle BCR[ Data Valid in next cycle End of row Don’t Care Max Input CLK Frequency (MHz) 133 104 66(15ns) 66(15ns) 104(9.62ns) 104(9.62ns) 133(7.5ns) ...
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... Cycle N Cycles AADV ACLK Valid Valid Output Output Valid Valid Input Input 27 EMC163SP16K 1Mx16 CellularRAM AD-MUX Undefined Don’t Care Max Input CLK Frequency (MHz) 104 83 33(30ns) 33(30ns) 52(19.2ns) 52(19.2ns) 66(15ns) 66(15ns) 75(13 ...
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... Note: 1. Reserved bits must be set to zero. Reserved bits not set to zero will affect device functionality. RCR[15:0] will be read back as written. A/DQ A/DQ A/DQ A/DQ [15: 15 Ignored Setting is ignored (Default 001b) 28 EMC163SP16K 1Mx16 CellularRAM AD-MUX A/DQ A/DQ A/ Reserved PAR Must be set to “0” RCR[2] RCR[1] RCR[0] ...
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... One-eighth of die E0000h-FFFFFh DIDR[14:11] DIDR[10:8] Device version Device density Bit Bit Density Setting Setting 2nd 0001b 16Mb 000b 29 EMC163SP16K 1Mx16 CellularRAM AD-MUX Size Density 1 Meg x 16 16Mb 512 8Mb 256 4Mb 128 2Mb 0 Meg x 16 0Mb 512 8Mb ...
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... I 2 104MHz CC 83MHz 133MHz = 0 OUT I 3R 104MHz CC 83MHz 133MHz I 3W 104MHz CC 83MHz or 0V, CE Standard CCQ SB 30 EMC163SP16K 1Mx16 CellularRAM AD-MUX Rating -0.3V to VccQ + 0.3V -0.2V to +2.45V -0.2V to +2.45V -55°C to +150°C -30°C to +85°C +260°C Min Max Unit Notes 1.7 1.95 V 1 CCQ CCQ -0 ...
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... Note: All tests are performed with the outputs configured for default setting of half drive strength (BCR[5:4] = 01b). Symbol Standard power (no or 0V, CE CCQ PAR designation) Symbol Test Points Test Points 50Ω DUT 30pF 31 EMC163SP16K 1Mx16 CellularRAM AD-MUX Array Partition Max Full 70 1/2 65 1 Min Max Unit Notes 2 3.0 6.5 pF ...
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... AVH t 5 AVS BHZ CVS OEW t OHZ t 3 OLZ toward VccQ/ EMC163SP16K 1Mx16 CellularRAM AD-MUX Max Unit Notes 7 ...
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... KOH OHZ OLZ refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# CEM or V toward VccQ/ EMC163SP16K 1Mx16 CellularRAM AD-MUX 83MHZ Unit Notes Max Min Max 35 ...
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... AVH t 5 AVS CPH t 7 CVS WHZ toward VccQ/ EMC163SP16K 1Mx16 CellularRAM AD-MUX Max Unit Notes ...
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... KHKL t 5.5 KHTL KOH refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# CEM or V toward VccQ/ EMC163SP16K 1Mx16 CellularRAM AD-MUX 83MHZ Unit Notes Max Min Max µ ...
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... CVS OLZ t t AVS AVH V OH Valid address OEW 36 EMC163SP16K 1Mx16 CellularRAM AD-MUX (MIN) Vcc Device ready for normal operation Max Unit µ 150 BHZ t OHZ Valid Output t HZ High-Z Don’t Care Undefined ...
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... CEM t t CSP ABA t BOE OLZ ACLK SP V Valid OH High-Z Valid Output Address KOH t KHTL t KHTL (WE# = HIGH) 37 EMC163SP16K 1Mx16 CellularRAM AD-MUX OHZ KOH High-Z High-Z Don’t Care Undefined ...
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... OLZ ACLK Valid Valid address Output KOH t KHTL t KHTL (WE# = HIGH) 38 EMC163SP16K 1Mx16 CellularRAM AD-MUX CBPH OHZ KOH Note 3 Valid Valid Valid Output Output Output Note 2 Undefined Don’t Care High-Z ...
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... HD t AADV t CEM t CSP AVH Valid Address KHTL (WE# = HIGH) 39 EMC163SP16K 1Mx16 CellularRAM AD-MUX KHKL OHZ t BOE t OLZ ACLK KOH High-Z Valid Output t KOH High-Z t KHTL Undefined Don’t Care ...
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... ACLK t AVH Valid Valid address Output KOH t KHTL t KHTL (WE# = HIGH) 40 EMC163SP16K 1Mx16 CellularRAM AD-MUX CBPH OHZ KOH Valid Valid Valid Output Output Output Undefined Don’t Care Note 3 High-Z ...
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... For burst READs, CE# must go HIGH before the second CLK after the WAIT period begins ( before the second CLK after WAIT asserts with BCR[8]=0, or before the third CLK after WAIT asserts with BCR[8]= CSP Note 2 End of row Valid Valid Output Output KHTL t KOH 41 EMC163SP16K 1Mx16 CellularRAM AD-MUX High-Z Undefined Don’t Care ...
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... Nondefault BCR settings for burst READ at end of row : fixed or variable latency, WAIT active LOW, WAIT asserted during delay. (shown as solid line) 2. WAIT will be assert for LC cycles for variables latency cycles for fixed latency. End of row t HD Valid output t KTHL Note 2 t KOH 42 EMC163SP16K 1Mx16 CellularRAM AD-MUX Valid output Valid output t KTHL t KOH Don’t Care Undefined ...
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... WE A/DQ[15: WAIT V OL Valid Address t t AVS AVH CVS AVS AVH Valid Address t AW High-Z 43 EMC163SP16K 1Mx16 CellularRAM AD-MUX Valid Input Don’t Care ...
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... CLK Valid Address CSP t CEM Valid Address D1 t KHTL KHTL Note 2 t KOH 44 EMC163SP16K 1Mx16 CellularRAM AD-MUX KHKL Don’t Care t CBPH Note4 t HZ High-Z ...
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... CE# must go HIGH before any clock edge following the last word of a defined-length burst. t CLK t SP Valid Address t AVH CSP t CEM AVH Valid Address KHTL SP KHTL Note2 t KOH 45 EMC163SP16K 1Mx16 CellularRAM AD-MUX KHKL Don’t Care t CBPH Note High-Z ...
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... For burst WRITEs, CE# must go HIGH before the second CLK after the WAIT period begins(before the second CLK after WAIT asserts with BCR[8]=0, or before the third CLK after WAIT asserts with BCR[8]=1 CSP Note Valid Valid Intput Intput End of row t KOH t KHTL 46 EMC163SP16K 1Mx16 CellularRAM AD-MUX High-Z Don’t Care Undefined ...
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... Nondefault BCR settings for burst WRITE at end of row : Fixed or variable latency, WAIT active LOW, WAIT asserted during delay. (shown as solid line) 2. WAIT will be assert for LC cycles for variables latency cycles for fixed latency. End of row t HD Valid input Valid input t KTHL t KOH Note 2 47 EMC163SP16K 1Mx16 CellularRAM AD-MUX Valid input Valid input t KTHL t KOH Don’t Care Undefined ...
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... CBPH Note Valid Address t CEM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# 48 EMC163SP16K 1Mx16 CellularRAM AD-MUX CSP BOE KOH HD V Valid Valid Valid OH Output Output Output ...
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... CE# HIGH CE# HIGH for longer than 15ns Valid Address CBPH CSP Note Data Valid Address KHTL 49 EMC163SP16K 1Mx16 CellularRAM AD-MUX t CLK BOE Valid Valid Valid Output Output Output ACLK t KOH Don’ ...
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... OHZ t BOE OLZ KOH HD ACLK V OH Valid Output KOH t KHTL 50 EMC163SP16K 1Mx16 CellularRAM AD-MUX Valid Address t t AVS AVH CBPH Note AVS ...
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... Otherwise, CPH is only required after CE#-controlled WRITEs. Valid Address t t AVS CVS t CPH Note 1 Valid Address Valid Input AVS DS DH High-Z 51 EMC163SP16K 1Mx16 CellularRAM AD-MUX AVH AADV t BHZ OLZ ...
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... U ----------------------- 3.0V S ----------------------- 2.5V R ----------------------- 2.0V P ----------------------- 1.8V L ----------------------- 1.5V 7. Organization 8 ---------------------- x8 bit 16 ---------------------- x16 bit 32 ---------------------- x32 bit EMC163SP16K 1Mx16 CellularRAM AD-MUX 7. Organization 8. Version Blank ----------------- Mother die A ----------------------- 2’nd generation B ----------------------- 3’rd generation C ----------------------- 4’th generation D ----------------------- 5’th generation 9. Option Blank ---- No optional mode ...