emc163sp16k Emlsi Inc., emc163sp16k Datasheet - Page 20

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emc163sp16k

Manufacturer Part Number
emc163sp16k
Description
1mx16 Bit Cellularram Ad-mux
Manufacturer
Emlsi Inc.
Datasheet
Figure 12: Register READ, Synchronous Mode, Followed by READ ARRAY Operation
Note:
1. Nondefault BCR settings for synchronous mode register READ followed by READ ARRAY operation: Latency code 2 (3 clocks),
2. A[19:18] = 00b to read RCR, 10b to read BCR, and 01b to read DIDR.
3. CE# must remain LOW to complete a burst-of-one READ. WAIT must be monitored; additional WAIT cycles caused by refresh collisions require
a corresponding number of additional CE# LOW cycles.
WAIT active LOW, WAIT asserted during delay.
(except A[19:18])
A/DQ[15:0]
A[19:18]
LB#/UB#
A[19:16]
ADV#
WAIT
WE#
CRE
CLK
OE#
CE#
2
Latch control register value
High-Z
t
t
t
CSP
t
SP
SP
SP
t
SP
t
KHTL
t
t
t
HD
HD
HD
t
ABA
t
Note3
OLZ
t
BOE
Latch control register address
t
ACLK
Valid CR
20
t
KOH
t
t
OHZ
HZ
t
HD
t
CBPH
High-Z
Address
Address
Address
1Mx16 CellularRAM AD-MUX
Don’t Care
EMC163SP16K
Undefined
Valid
data

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