emc163sp16k Emlsi Inc., emc163sp16k Datasheet - Page 44
emc163sp16k
Manufacturer Part Number
emc163sp16k
Description
1mx16 Bit Cellularram Ad-mux
Manufacturer
Emlsi Inc.
Datasheet
1.EMC163SP16K.pdf
(52 pages)
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Figure 31: Burst WRITE Operation - Variable Latency Mode
Note:
1. Nondefault BCR settings for burst WRITE operation in variable latency mode: latency code 2 (3 clocks), WAIT active LOW, WAIT asserted
2. WAIT asserts for LC cycles for both fixed and variable latency. LC = latency code (BCR[13:11]).
3.
4. CE# must go HIGH before any clock edge following the last word of a defined-length burst.
during delay, burst length 4, burst wrap enabled.
t
AS required if
A/DQ[15:0]
UB#/LB#
A[19:16]
WAIT
ADV#
WE#
CE#
OE#
CLK
t
CSP > 20ns.
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
IH
IL
IH
IH
IL
IH
IL
OH
OL
IH
IL
IH
IL
IH
IL
IH
IL
IL
t
AS
t
t
AS
AS
High-Z
3
3
3
WRITE Burst Identified
(WE# = Low)
t
t
t
t
CSP
Valid Address
SP
SP
SP
Valid Address
t
SP
t
KHTL
t
t
HD
HD
t
t
HD
HD
Note 2
t
CEM
44
t
KHTL
t
KOH
t
SP
t
CLK
t
SP
D1
t
HD
t
HD
t
KHKL
D2
1Mx16 CellularRAM AD-MUX
D3
t
KP
EMC163SP16K
t
KP
D0
t
HD
Don’t Care
t
HZ
Note4
t
CBPH
High-Z
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