emc643sp16ak Emlsi Inc., emc643sp16ak Datasheet
emc643sp16ak
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emc643sp16ak Summary of contents
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... Tel : +82-64-740-1700 Fax : +82-64-740-1749~1750 / Homepage : www.emlsi.com The attached datasheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your questions about device. If you have any questions, please contact the EMLSI office. EMC643SP16AK 4Mx16 CellularRAM AD-MUX Date Feb ...
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... Partial array refresh (PAR) OPTIONS - Configuration: 64Mb (4 megabit x 16) - Vcc core / VccQ I/O voltage supply: 1.8V - Timing: 70ns access - Frequency: 83 MHz, 104 MHz, 133 MHz - Standby current at 85°C : 140µA(max) - Operating temperature range: Wireless -30°C to +85°C EMC643SP16AK 4Mx16 CellularRAM AD-MUX 2 ...
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... Drive Strength (BCR[5:4]) Default = Outputs Use Half-Drive Strength ...................................................................................... 25 WAIT Polarity (BCR[10]) Default = WAIT Active HIGH.............................................................................................................. 26 Initial Access Latency (BCR[14]) Default = Variable.................................................................................................................. 26 Operating Mode (BCR[15]) Default = Asynchronous Operation................................................................................................ 28 Refresh Configuration Register...................................................................................................................................................... 28 Device Identification Register......................................................................................................................................................... 29 Electrical Characteristics.................................................................................................................................................................... 30 Timing Requirements.......................................................................................................................................................................... 32 Timing Diagrams................................................................................................................................................................................. 36 EMC643SP16AK 4Mx16 CellularRAM AD-MUX 3 ...
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... Figure 33: Burst WRITE Terminate at End-of-Row (Wrap off) ............................................................................................................ 46 Figure 34: Burst WRITE Row Boundary Crossing .............................................................................................................................. 47 Figure 35: Burst WRITE Followed by Burst READ .............................................................................................................................. 48 Figure 36: Asynchronous WRITE Followed by Burst READ ............................................................................................................... 49 Figure 37: Burst READ Followed by Asynchronous WRITE ............................................................................................................... 50 Figure 38: Asynchronous WRITE Followed by Asynchronous READ ................................................................................................. 51 EMC643SP16AK 4Mx16 CellularRAM AD-MUX 4 ...
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... Table 10: Electrical Characteristics and Operating Conditions ....................................................................................................... 30 Table 11: Partial-Array Specifications and Conditions .................................................................................................................... 31 Table 12: Capacitance .................................................................................................................................................................... 31 Table 13: Asynchronous READ Cycle Timing Requirements ......................................................................................................... 32 Table 14: Burst READ Cycle Timing Requirements ........................................................................................................................ 33 Table 15: Asynchronous WRITE Cycle Timing Requirements ........................................................................................................ 34 Table 16: Burst WRITE Cycle Timing Requirements ...................................................................................................................... 35 Table 17: Initialization Timing Parameters ...................................................................................................................................... 36 EMC643SP16AK 4Mx16 CellularRAM AD-MUX 5 ...
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... Note: Functional block diagrams illustrate simplified device operation. See pin descriptions; Bus operations table; and timing diagrams for detailed information. Address Decode 4,096K x 16 Logic DRAM MEMORY ARRAY Refresh Configuration Register (RCR) Device ID Register (DIDR) Bus Configuration Register (BCR) Internal 6 EMC643SP16AK 4Mx16 CellularRAM AD-MUX Input Output A/DQ[7:0] MUX and A/DQ[15:8] Buffers External ...
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... I/O power supply: (1.70V.1.95V) Power supply for input/output buffers. VSS Supply VSS must be connected to ground. VSSQ Supply VSSQ must be connected to ground. Note: 1. When using asynchronous mode exclusively, CLK can be tied to VSSQ or VCCQ. WAIT should be ignored during asynchronous mode operations. EMC643SP16AK 4Mx16 CellularRAM AD-MUX Descriptions 7 ...
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... Idle EMC643SP16AK 4Mx16 CellularRAM AD-MUX UB#/ WE# CRE WAIT2 A/DQ[15:0] LB Low-z Data out High-z Data High-z High Low Low-z High-z Config ...
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... Until the end of VccQ and remain HIGH. When initialization is complete, the device is ready for normal operation. Figure 2: Power-Up Initialization Timing Vcc=1.7V Vcc VccQ 4Mx16 CellularRAM AD-MUX t PU Device ready for normal operation Device Initialization 9 EMC643SP16AK t PU, CE# should track ...
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... A/DQ bus. The data to be written is latched on the rising edge of CE#, WE#, UB#, or LB# (whichever occurs first). During asynchronous operations with burst mode enabled, the CLK input must be held static(HIGH or LOW). WAIT will be driven during asynchronous READs, and its state should be ignored. WE# LOW time must be limited to tCEM. EMC643SP16AK 4Mx16 CellularRAM AD-MUX 10 ...
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... Figure 3: READ Operation A[21:16] CE# OE# WE# A/DQ[15:0] ADV# LB#/UB# Figure 4: WRITE Operation A[21:16] CE# OE# WE# A/DQ[15:0] ADV# LB#/UB# Valid Address Valid High-Z Address Valid Address Valid Address Don’t Care 11 EMC643SP16AK 4Mx16 CellularRAM AD-MUX Valid Data Don’t Care t CEM Valid Data Undefined ...
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... Non-default BCR settings for burst mode READ (4-word burst): Fixed or variable latency; Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. Diagram in the figure above is representative of variable latency with no refresh collision or fixed-latency access EMC643SP16AK 4Mx16 CellularRAM AD-MUX Address Address READ Burst Identified (WE# = HIGH) Undefined Don’t Care ...
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... CE# should be taken HIGH and the burst restarted with a new CE# LOW/ADV# LOW cycle. CEM EMC643SP16AK 4Mx16 CellularRAM AD-MUX Address Address WRITE Burst Identified (WE# = LOW) Don’t Care . If a burst suspension will cause CE# to remain LOW CEM ...
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... Additional WAIT states inserted to allow refresh completion. Note: Non-default BCR settings for refresh collision during variable-latency READ operation: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay EMC643SP16AK 4Mx16 CellularRAM AD-MUX Don’t Care Undefined ...
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... LB# and UB# are disabled (HIGH) during an operation, the device will disable the data bus from receiving or transmitting data. Although the device will seem to be deselected, it remains in an active mode as long as CE# remains LOW. CellularRAM WAIT READY WAIT WAIT Other Other Device Device 15 EMC643SP16AK 4Mx16 CellularRAM AD-MUX . Mixed-mode operation CEM External Pull-Up Pull-Down Resistor ...
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... Table 7 on page 29). READ and WRITE operations to address ranges receiving refresh will not be affected. Data stored in addresses not receiving refresh will become corrupted. When re-enabling additional portions of the array, the new portions are available immediately upon writing to the RCR. EMC643SP16AK 4Mx16 CellularRAM AD-MUX 16 ...
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... CRE t ADV# CE# Initiate Control register access OE# WE# LB#/UB# OPCODE A/DQ[15:0] Note: A[19:18] = 00b to load RCR, and 10b to load BCR. t AVH AVS t AVH Write address bus value to control register 17 EMC643SP16AK 4Mx16 CellularRAM AD-MUX Address Address t CPH Valid Address data Don’t Care ...
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... A[19:18] = 00b to load RCR, and 10b to load BCR. 3. CE# must remain LOW to complete a burst-of-one WRITE. WAIT must be monitored; additional WAIT cycles caused by refresh collisions require a corresponding number of additional CE# LOW cycles. Latch control register address Note3 18 EMC643SP16AK 4Mx16 CellularRAM AD-MUX Address Address t CBPH ...
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... Note: A[19:18] = 00b to read RCR, 10b to read BCR, and 01b to read DIDR. t AVH t t AVH AA AVS AADV Initiate register access OLZ Valid CR 19 EMC643SP16AK 4Mx16 CellularRAM AD-MUX Address Address t CPH OHZ t BHZ Address Don’t Care Valid data Undefined ...
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... CE# must remain LOW to complete a burst-of-one READ. WAIT must be monitored; additional WAIT cycles caused by refresh collisions require a corresponding number of additional CE# LOW cycles. Latch control register address t CBPH t ABA Note3 OHZ BOE KOH ACLK OLZ Valid CR High-Z 20 EMC643SP16AK 4Mx16 CellularRAM AD-MUX Address Address Address Undefined Don’t Care Valid data ...
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... The use of the software sequence does not affect the ability to perform the standard (CRE-controlled) method of loading the configuration registers. However, the software nature of this access mechanism eliminates the need for CRE. If the software mechanism is used, CRE can simply be tied to VSS. The port line often used for CRE control purposes is no longer required. EMC643SP16AK 4Mx16 CellularRAM AD-MUX 21 ...
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... If the data at the falling edge of WE# is not 0000h, 0001h or 0002h possible that the data stored at the highest memory location will be altered. READ Address (MAX) Address Address XXXX XXXX (MAX) (MAX) READ Address (MAX) Address XXXX XXXX (MAX) 22 EMC643SP16AK 4Mx16 CellularRAM AD-MUX WRITE WRITE Address Address (MAX) (MAX) 0ns (min); Note 1 Address CR Value (MAX) in RCR : 0000h BCR : 0001h READ WRITE Address ...
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... Code 1 - Reserved 0 Code 2 1 Code 3 (default) 0 Code 4 1 Code 5 0 Code 6 1 Code 7 - Reserved BCR[10] WAIT Polarity 0 Active LOW 1 Active HIGH (default) 23 EMC643SP16AK 4Mx16 CellularRAM AD-MUX A/DQ A/DQ A/DQ A/ [5: WAIT Drive Reserved Reserved Configuration(WC) Strength Must be set to “0” Must be set to “0” ...
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... EMC643SP16AK 4Mx16 CellularRAM AD-MUX 32 Word Continuous Burst Length Burst Linear Linear 0-1-2 ... 29-30-31 0-1-2-3-4-5-6-... 1-2-3 ... 30-31-0 1-2-3-4-5-6-7-... 2-3-4 ... 31-0-1 2-3-4-5-6-7-8-... 3-4-5 ... 0-1-2 3-4-5-6-7-8-9-... 4-5-6 ... 1-2-3 4-5-6-7-8-9-10-... 5-6-7 ... 2-3-4 5-6-7-8-9-10-11-... 6-7-8 ... 3-4-5 6-7-8-9-10-11-12-... 7-8-9 ... 4-5-6 7-8-9-10-11-12-13-... ... ... 14-15-16-...-11-12-13 14-15-16-17-18-19-20-... 15-16-17...-12-13-14 15-16-17-18-19-20-21-... ... ... 30-31-0-...-27-28-29 30-31-32-33-34-... ...
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... See Table 4 for additional information. Table 4: Drive Strength BCR[5] BCR[ Drive Strength Impedance Typ (Ω ) Full 25~30 1/2 50 (default) 1/4 100 25 EMC643SP16AK 4Mx16 CellularRAM AD-MUX Use Recommendation CL = 30pF to 50pF CL = 15pF to 30pF 104 MHz at light load CL = 15pF or lower Reserved ...
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... D2 D3 End of row 1 Latency Normal Refresh Collision EMC643SP16AK 4Mx16 CellularRAM AD-MUX BCR[ Data Valid in current cycle BCR[ Data Valid in next cycle Don’t Care Max Input CLK Frequency (MHz) 133 104 83 66(15ns) 66(15ns) 52(19.2ns) 104(9.62ns) 104(9.62ns) 83(12ns) 133(7 ...
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... N-1 Cycle N Cycles AADV ACLK Valid Output Valid Valid Input Input 27 EMC643SP16AK 4Mx16 CellularRAM AD-MUX Don’t Care Undefined Max Input CLK Frequency (MHz) 133 104 33(30ns) 33(30ns) 52(19.2ns) 52(19.2ns) ...
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... Note: 1. Reserved bits must be set to zero. Reserved bits not set to zero will affect device functionality. RCR[15:0] will be read back as written. A/DQ A/DQ A/DQ [15: 15 Reserved Ignored Setting is ignored (Default 001b) 28 EMC643SP16AK 4Mx16 CellularRAM AD-MUX A/DQ A/DQ A/ Reserved Must be set to “0” RCR[2] RCR[1] ...
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... One-eighth of die 380000h-3FFFFFh DIDR[14:11] DIDR[10:8] Device version Device density Bit Version Density Setting 2nd 0001b 64Mb 29 EMC643SP16AK 4Mx16 CellularRAM AD-MUX Size 4 Meg Meg Meg x 16 512 Meg Meg Meg x 16 512 DIDR[7:5] CellularRAM generation Bit ...
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... IH LO Conditions chip enabled CCQ OUT 0V, CE CCQ CCQ SB 30 EMC643SP16AK 4Mx16 CellularRAM AD-MUX Rating -0.3V to VccQ + 0.3V -0.2V to +2.45V -0.2V to +2.45V -55°C to +150°C -30°C to +85°C +260°C Symbol Min 1 CCQ -0.20 IL 0.80 V CCQ Symbol ...
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... Note: All tests are performed with the outputs configured for default setting of half drive strength (BCR[5:4] = 01b). Conditions = V or 0V, CE CCQ CCQ PAR Conditions +25° MHz Test Points Test Points 50Ω DUT 30pF 31 EMC643SP16AK 4Mx16 CellularRAM AD-MUX Symbol Array Partition Full 1/2 Standard power (no 1/4 designation ) 1/8 0 Symbol Min Max C 2 ...
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... AVH t 5 AVS BHZ CVS OEW t OHZ t 3 OLZ toward VccQ/ EMC643SP16AK 4Mx16 CellularRAM AD-MUX Max Unit 7 Notes ...
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... KHTL t 2 KOH OHZ t 3 OLZ refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# CEM or V toward VccQ/ EMC643SP16AK 4Mx16 CellularRAM AD-MUX 104MHz 83MHZ Min Max Min Max 35 ...
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... AVH t 5 AVS CPH t 7 CVS WHZ toward VccQ/ EMC643SP16AK 4Mx16 CellularRAM AD-MUX Max Unit Notes ...
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... CSP t 1 1.2 KHKL t 5.5 KHTL refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# CEM or V toward VccQ/ EMC643SP16AK 4Mx16 CellularRAM AD-MUX 104MHz 83MHZ Min Max Min Max 9. 1.6 1 ...
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... CVS OLZ t t AVS AVH V OH Valid address OEW 36 EMC643SP16AK 4Mx16 CellularRAM AD-MUX (MIN) Vcc Device ready for normal operation Min Max 150 BHZ t OHZ Valid Output t HZ High-Z Undefined Don’t Care Unit µ ...
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... CSP ABA t BOE OLZ ACLK SP V Valid OH High-Z Address KOH t KHTL t KHTL READ Burst Identified (WE# = HIGH) 37 EMC643SP16AK 4Mx16 CellularRAM AD-MUX OHZ KOH High-Z Valid Output High-Z Don’t Care Undefined ...
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... OLZ ACLK Valid OH address KOH t KHTL t KHTL READ Burst Identified (WE# = HIGH) 38 EMC643SP16AK 4Mx16 CellularRAM AD-MUX CEM t KOH Valid Valid Valid Output Output Output Output Don’t Care CBPH OHZ t HD Note 3 ...
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... SP t AADV t CEM t CSP AVH SP V Valid Address V t KHTL READ Burst Identified (WE# = HIGH) 39 EMC643SP16AK 4Mx16 CellularRAM AD-MUX KHKL OHZ t BOE t OLZ ACLK KOH OH Valid Output OL t KOH t KHTL Don’t Care ...
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... OLZ ACLK t AVH Valid address KOH t KHTL t KHTL READ Burst Identified (WE# = HIGH) 40 EMC643SP16AK 4Mx16 CellularRAM AD-MUX CEM t KOH Valid Valid Valid Valid Output Output Output Output Don’t Care CBPH OHZ t ...
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... For burst READs, CE# must go HIGH before the second CLK after the WAIT period begins ( before the second CLK after WAIT asserts with BCR[8]=0, or before the third CLK after WAIT asserts with BCR[8]= CLK CSP Note 2 End of row Valid Valid Output Output KHTL t KOH 41 EMC643SP16AK 4Mx16 CellularRAM AD-MUX High-Z Undefined Don’t Care ...
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... Nondefault BCR settings for burst READ at end of row : fixed or variable latency, WAIT active LOW, WAIT asserted during delay. (shown as solid line) 2. WAIT will be assert for LC cycles for variables latency cycles for fixed latency. End of row t HD Valid output t KTHL Note 2 t KOH 42 EMC643SP16AK 4Mx16 CellularRAM AD-MUX Valid output Valid output t KTHL t KOH Don’t Care Undefined ...
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... WE A/DQ[15: WAIT V OL Valid Address t t AVS AVH CVS AVS AVH Valid Address t AW High-Z 43 EMC643SP16AK 4Mx16 CellularRAM AD-MUX Valid Input Don’t Care ...
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... CLK Valid Address CSP t CEM Valid Address t KHTL KHTL Note 2 t KOH 44 EMC643SP16AK 4Mx16 CellularRAM AD-MUX KHKL CBPH Note4 t HZ High-Z Don’t Care ...
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... CLK t SP Valid Address t AVH CSP t CEM AVH Valid Address KHTL SP KHTL Note2 t KOH (WE# = LOW) 45 EMC643SP16AK 4Mx16 CellularRAM AD-MUX KHKL CBPH Note High-Z Don’t Care ...
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... For burst WRITEs, CE# must go HIGH before the second CLK after the WAIT period begins(before the second CLK after WAIT asserts with BCR[8]=0, or before the third CLK after WAIT asserts with BCR[8]=1). t CLK Note Valid Valid Input Input End of row t KOH t KHTL 46 EMC643SP16AK 4Mx16 CellularRAM AD-MUX CSP Don’t Care High-Z Undefined ...
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... Nondefault BCR settings for burst WRITE at end of row : Fixed or variable latency, WAIT active LOW, WAIT asserted during delay. (shown as solid line) 2. WAIT will be assert for LC cycles for variables latency cycles for fixed latency. End of row t HD Valid input Valid input t KTHL t KOH Note 2 47 EMC643SP16AK 4Mx16 CellularRAM AD-MUX Valid input Valid input t KTHL t KOH Don’t Care Undefined ...
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... HIGH CE# HIGH for longer than 15ns CBPH Note CEM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# 48 EMC643SP16AK 4Mx16 CellularRAM AD-MUX Valid Address CSP ...
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... READs. A refresh opportunity must be provided every either of the following two conditions: a) clocked CE# HIGH CE# HIGH for longer than 15ns. Valid Address t CBPH Note Data EMC643SP16AK 4Mx16 CellularRAM AD-MUX t CLK ...
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... CLK BOE OLZ KOH HD ACLK V OH Valid Output KOH t KHTL 50 EMC643SP16AK 4Mx16 CellularRAM AD-MUX Valid Address t t AVS AVH CBPH Note 2 t OHZ ...
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... When configured for synchronous mode (BCR[15] = 0), CE# must remain HIGH for at least 5ns ( t interval. Otherwise, CPH is only required after CE#-controlled WRITEs CVS BW t CPH CW Note 1 Valid Input High-Z 51 EMC643SP16AK 4Mx16 CellularRAM AD-MUX Valid Address t t AVS AVH AADV OLZ ...
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... S ----------------------- Single Transistor 6. Operating Voltage V ----------------------- 3.3V U ----------------------- 3.0V S ----------------------- 2.5V R ----------------------- 2.0V P ----------------------- 1.8V L ----------------------- 1.5V 7. Organization 8 ---------------------- x8 bit 16 ---------------------- x16 bit 32 ---------------------- x32 bit EMC643SP16AK 4Mx16 CellularRAM AD-MUX 8. Version Blank ----------------- Mother die A ----------------------- 2’nd generation B ----------------------- 3’rd generation C ----------------------- 4’th generation D ----------------------- 5’th generation 9. Option Blank ---- No optional mode J ------------ Non-RBC K ------------ RBC L ------------ 8 page mode / DPD ...