emc643sp16ak Emlsi Inc., emc643sp16ak Datasheet - Page 20
emc643sp16ak
Manufacturer Part Number
emc643sp16ak
Description
4mx16 Bit Cellularram Ad-mux
Manufacturer
Emlsi Inc.
Datasheet
1.EMC643SP16AK.pdf
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Figure 12: Register READ, Synchronous Mode, Followed by READ ARRAY Operation
Note:
1. Nondefault BCR settings for synchronous mode register READ followed by READ ARRAY operation: Latency code 2 (3 clocks),
2. A[19:18] = 00b to read RCR, 10b to read BCR, and 01b to read DIDR.
3. CE# must remain LOW to complete a burst-of-one READ. WAIT must be monitored; additional WAIT cycles caused by refresh collisions require
a corresponding number of additional CE# LOW cycles.
WAIT active LOW, WAIT asserted during delay.
(except A[19:18])
A/DQ[15:0]
A[19:18]
LB#/UB#
A[21:16]
ADV#
WAIT
WE#
CLK
CRE
OE#
CE#
2
Latch control register value
High-Z
t
CSP
t
t
t
SP
SP
SP
t
SP
t
KHTL
t
t
t
HD
HD
HD
t
ABA
t
Note3
OLZ
t
BOE
Latch control register address
t
ACLK
20
t
KOH
Valid CR
t
t
OHZ
HZ
t
HD
t
CBPH
High-Z
Address
Address
Address
4Mx16 CellularRAM AD-MUX
Don’t Care
EMC643SP16AK
Undefined
Valid
data
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