EMD56164P Emlsi Inc., EMD56164P Datasheet - Page 8

• Manufacturer Part Number: EMD56164P
• Description: 256m 16m X 16 Mobile Ddr Sdram
• Manufacturer: Emlsi Inc.

1. IDD specifications are tested after the device is properly initialized
2. Input slew rate is 1V/ns.
3. Definitions for IDD:
Table 7: AC OPERATING TEST CONDITIONS
(V
NOTE :
1. Under all conditions, VDDQ must be less than or equal to VDD.
2. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation.
3. CK and CKB crossing voltage.
AC input levels(Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Vix
Output load condition
LOW is defined as V
HIGH is defined as V
STABLE is defined as inputs stable at a HIGH or LOW level ;
SWITCHING is defined as :
DD
- address and command : inputs changing between HIGH and LOW once per two clock cycles ;
- data bus inputs : DQ changing between HIGH and LOW once per clock cycle ; DM and DQS are STABLE
Output
= 1.7V ~ 1.95V, T
Figure 1. DC Output Load Circuit
10.6㏀
Parameter
IN
IN
≤ 0.1 * VDDQ ;
≥ 0.9 * VDDQ ;
A
= -25℃ ~85℃ for Extended)
1.8V
13.9㏀
20㎊
V
V
OH
OL
(DC) = 0.1 × V
(DC) = 0.9 × V
NOTE :
DDQ
DDQ
0.4 × V
, I
, I
OL
OH
0.8 × V
= 0.1 ㎃
DDQ
= -0.1㎃
8
(Min) / 0.6 × V
See Figure 2
0.5 × V
0.5 × V
DDQ
Value
1.0
/ 0.2 × V
Output
DDQ
DDQ
Figure 2. AC Output Load Circuit
DDQ
DDQ
256M: 16M x 16 Mobile DDR SDRAM
(Max)
Z0=50Ω
Unit
V/㎱
V
V
V
V
EMD56164P
Preliminary
Vtt=0.5 × V
50Ω
20㎊
Note
3
Rev 0.0
DDQ