cs47028-dqz Cirrus Logic, Inc., cs47028-dqz Datasheet
cs47028-dqz
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cs47028-dqz Summary of contents
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... SPI Configurable GPIOs and External Interrupt Input 1.8V Core and a 3.3V I/O that is tolerant to 5V input Low-power Mode “†” Feature may differ on CS47024, CS47028, or CS47048. See Table 2. ADC’s & DAC’s operate in Single ended or Differential mode Stereo Inputs ...
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... SRS CircleSurround II technology is incorporated under license from SRS Labs, Inc. The SRS TruVolume technology/solution rights incorporated in the Cirrus Logic CS470xx products are owned by SRS Labs, a U.S. Corporation and licensed to Cirrus Logic, Inc. Purchaser of the Cirrus Logic CS470xx products must sign a license for use of the chip and display of the SRS Labs trademarks. Any products incorporating the Cirrus Logic CS470xx products must be sent to SRS Labs for review. SRS CircleSurround II is protected under US and foreign patents issued and/or pending ...
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Table of Contents FEATURES ......................................................................................................................... 1 1. Documentation Strategy .........................................................................................................6 2. Overview ..................................................................................................................................6 2.1 Licensing ............................................................................................................................................... 6 3. Code Overlays .........................................................................................................................7 4. Hardware Functional Description .......................................................................................10 4.1 Coyote 32-bit DSP Core ...................................................................................................................... 12 4.2 DSP Memory ....................................................................................................................................... 12 4.2.1 DMA ...
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... Gain Error .......................................................................................................................................... 38 10.7 Gain Drift ........................................................................................................................................... 38 11. Revision History ..................................................................................................................39 Figures Figure 1. CS47048 Top-Level Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 2. CS47028 Top-Level Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 3. CS47024 Top-Level Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 4. RESET Timing at Power- Figure 5. RESET Timing after Power is Stable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 6. XTI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 7. Serial Control Port - SPI Slave Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 8 ...
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Table 3. CS470xx Channel Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... CS470xx Data Sheet Audio SOC Processor Family 1. Documentation Strategy The CS470xx Data Sheet describes the CS47048, CS47028, and CS47024 audio processors. This document should be used in conjunction with the following documents when evaluating or designing a system around the CS470xx processors Table 1. Document Name CS470xx Data Sheet CS470xx Hardware User’ ...
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Code Overlays The suite of software available for the CS470xx family consists of an operating system (OS) and a library of overlays. The software components for the CS470xx family include: 1. OS/Kernel—Encompasses all non-audio processing tasks, including loading data ...
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... DSP Tool Set w/ Private Keys Protect Customer IP • Configurable GPIOs and External Interrupts • Hardware Watchdog Timer 8 CS470xx Device Selection Guide CS47028-CQZ CS47028-DQZ • 2-In/8-Out Car Audio • Sound Bar • DVD Receiver 100-pin LQFP with Exposed Pad Cirrus Logic 32-bit Core • ...
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... CS47048 channels • 1 TDM line channels per line. 2 • lines, 2 channels per line CS47028 channels • 1 TDM line channels per line. 2 • lines, 2 channels per line CS47024 channels • 1 TDM line, ...
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... Audio SOC Processor Family 4. Hardware Functional Description The CS470xx family, which includes the CS47048, CS47028, and CS47024 DSPs true system-on-a-chip that combines a powerful 32-bit DSP engine with analog/digital audio inputs and analog/digital audio outputs. It can be integrated into a complex multi-DSP processing system, or stand alone in an audio product that requires analog-in and analog-out ...
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... DMA ROM 4ch X RAM PIC ROM ROM Y P RAM RAM 32K x 32-bit SRAM with three 2K blocks Assignable to Program or Y Data memory CS47028 Top-Level Block Diagram Clock DBC PLL Timers Manager Slave) Cirrus 32-bit Core text in the CS 47024 DSP x8 DMA ROM ...
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CS470xx Data Sheet Audio SOC Processor Family 4.1 Cirrus Logic 32-bit DSP Core The CS470xx comes with a Cirrus Logic 32-bit core with separate X and Y data and P code memory spaces. The DSP core is a high-performance, 32-bit, ...
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... Please see Section 5.16 “ADC Characteristics” on page 27 performance. The CS47024 and CS47028 devices support simultaneous channels of analog-to-digital conversion with the input source selectable using an integrated 5:1 stereo analog mux (analog inputs AIN_2A/B through AIN_6A/B). The CS47048 device adds a second pair of ADCs that are directly connected to input pins AIN_1A/B providing a total of 4 simultaneous channels of analog-to-digital conversion ...
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... SRC can convert channels of audio data from the one input sample rate (Fsi) to another output sample rate (Fso). The CS47028 and CS47048 devices have an additional stand-alone 8-channel SRC module. This SRC module can be used to make independent input clock domains synchronous (different Fs on PCM input and S/PDIF Rx) ...
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Termination Requirements Open-drain pins on the CS470xx must be pulled high for proper operation. Please refer to the CS470xx Hardware User’s Manual to identify which pins are open-drain and what value of pull-up resistor is required for proper operation. ...
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CS470xx Data Sheet Audio SOC Processor Family 5. Characteristics and Specifications All data sheet minimum and maximum timing parameters are guaranteed over the rated voltage and Note: temperature. All data sheet typical parameters are measured under the following conditions: T ...
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Power Supply Characteristics Note: Measurements performed under operating conditions) Parameter Operational Power Supply Current: 1 VDD: Core and I/O operating VDDA: PLL operating current VDDA: DAC operating current (all 8 channels enabled) VDDA: ADC operating current (all 4 channels ...
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CS470xx Data Sheet Audio SOC Processor Family 5.6 Digital Switching Characteristics— RESET Parameter 1 RESET minimum pulse width low All bidirectional pins high-Z after RESET low Configuration pins setup before RESET high Configuration pins hold after RESET high 1.The rising ...
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... Digital Switching Characteristics — Internal Clock Parameter 1 Internal DSP_CLK frequency CS47048-CQZ CS47048-DQZ CS47028-CQZ CS47028-DQZ CS47024-CQZ CS47024-DQZ 1 Internal DSP_CLK period CS47048-CQZ CS47048-DQZ CS47028-CQZ CS47028-DQZ CS47024-CQZ CS47024-DQZ 1. After initial power-on reset, F dclk locked until the next power-on reset. 2. See Section 5.7. for all references to F DS787PP5 Symbol 1 F xtal T ...
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CS470xx Data Sheet Audio SOC Processor Family 5.9 Digital Switching Characteristics — Serial Control Port - SPI Slave Mode Parameter 1 SCP_CLK frequency SCP_CS falling to SCP_CLK rising SCP_CLK low time SCP_CLK high time Setup time SCP_MOSI input Hold time ...
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Digital Switching Characteristics — Serial Control Port - SPI Master Mode Parameter 1,2 SCP_CLK frequency 3 EE_CS falling to SCP_CLK rising SCP_CLK low time SCP_CLK high time Setup time SCP_MISO input Hold time SCP_MISO input SCP_CLK low to SCP_MOSI ...
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CS470xx Data Sheet Audio SOC Processor Family 5.11 Digital Switching Characteristics — Serial Control Port - I Parameter 1 SCP_CLK frequency SCP_CLK rise time SCP_CLK fall time SCP_CLK low time SCP_CLK high time SCP_CLK rising to SCP_SDA rising or falling ...
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Digital Switching Characteristics — Serial Control Port - I Parameter 1 SCP_CLK frequency SCP_CLK rise time SCP_CLK fall time SCP_CLK low time SCP_CLK high time SCP_CLK rising to SCP_SDA rising or falling for START or STOP condition START condition ...
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CS470xx Data Sheet Audio SOC Processor Family 5.13 Digital Switching Characteristics — Digital Audio Slave Input Port Parameter DAI_SCLK period DAI_SCLK duty cycle Setup time DAI_DATAn Hold time DAI_DATAn DAI_SCLK DAI_DATAn Figure 11 daidsu daidh Digital Audio ...
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Digital Switching Characteristics — Digital Audio Output Port Parameter DAO_MCLK period DAO_MCLK duty cycle DAO_SCLK period for Master or Slave mode DAO_SCLK duty cycle for Master or Slave mode Master Mode (Output A1 Mode) DAO_SCLK delay from DAO_MCLK rising ...
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CS470xx Data Sheet Audio SOC Processor Family t daosclk DAO_SCLK t daoslrts DAO_LRCLK t DAOn_DATAn A. DAO_LRCLK transition before DAO_SCLK non-active edge. See Footnote 3 on page 25. Figure 13. 5.15 Digital Switching Characteristics — S/PDIF RX Port (Inputs: Logic ...
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... This number was measured using perfectly matched external resistors (R typically reduce CMRR by 20 log (| 9. C represents the parasitic load capacitance between R L package. 10. This measurement is not applicable to the CS47028 and CS47024 devices. DS787PP5 = 0 to +70C; VDD = 1.8V±5%, VDDA (VA)= 3.3V±5%; 1 kHz sine A =10 k) in Figure 14 on page 29 ...
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... This number was measured using perfectly matched external resistors (R typically reduce CMRR by 20 log (| 9. C represents the parasitic load capacitance between R L package. 10. This measurement is not applicable to the CS47028 and CS47024 devices -40 to +85C; VDD = 1.8V±5%, VDDA (VA)= 3.3V±5%; 1 kHz A =10 k) in Figure 14 on page 29 ...
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AIN Figure 14. AIN- AIN+ Figure 15. DS787PP5 10µ AIN_xA+ AIN_xB+ 100K C L ADC Single-Ended Input Test Circuit 10µ AIN_xA- or AIN_xB- 100K C L 10µ AIN_xA+ or AIN_xB+ 100K ...
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CS470xx Data Sheet Audio SOC Processor Family 5.16.3 ADC Digital Filter Characteristics Parameter kHz Passband (Frequency Response) Passband Ripple Stopband Stopband Attenuation Total Group Delay High-Pass Filter Characteristics Frequency Response-3.0 dB -0.13 dB Phase Deviation @ 20 ...
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Analog Output Characteristics (Automotive) Test Conditions (unless otherwise specified): T sine wave driven through a filter shown in tion; Measurement Bandwidth kHz. Parameter kHz Dynamic Range A-weighted unweighted Total Harmonic Distortion ...
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CS470xx Data Sheet Audio SOC Processor Family AOUT_x- AOUT_x output output: R Figure 17. 125 100 5.17.3 Combined DAC Interpolation & On-chip Analog Filter Response Parameter Passband (Frequency Response) Frequency Response ...
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... NOTE: Please contact the factory for availability of the -D (automotive grade) package. 7. Environmental, Manufacturing, & Handling Information Table 6. Environmental, Manufacturing, and Handling Information Model Number CS47048C-CQZ CS47048C-DQZ CS47028C-CQZ CS47028C-DQZ CS47024C-CQZ CS47024C-DQZ * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. DS787PP5 Table 5. Ordering Information Grade Temp ...
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CS470xx Data Sheet Audio SOC Processor Family 8. Device Pinout Diagram 8.1 CS47048, 100-Pin LQFP Pinout Diagram 1 DBCK DBDA GPIO15, DAI_LRCLK GPIO17, DAI_SCLK VDDIO1 5 GNDIO1 GPIO16, DAI_DATA0, TM0 GPIO0, DAI_DATA1, TM1 GPIO1, DAI_DATA2, TM2 GPIO2, DAI_DATA3, TM3, SPDIF ...
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... CS47028, 100-Pin LQFP Pinout Diagram DBCK 1 DBDA GPIO15, DAI_LRCLK GPIO17, DAI_SCLK 5 VDDIO1 GNDIO1 GPIO16, DAI_DATA0, TM0 GPIO0, DAI_DATA1, TM1 GPIO1, DAI_DATA2, TM2 10 GPIO2, DAI_DATA3, TM3, SPDIF RX VDD1 GND1 GPIO7, DAO_LRCLK GPIO14, DAO_SCLK GNDIO2 15 VDDIO2 GPIO18, DAO_MCLK, HS4 GPIO6, DAO_DATA0, HS0 GPIO3, DAO_DATA1, HS1 ...
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... GPIO5, DAO_DATA3, HS3, S/PDIF TXa VDD2 GND2 GPIO9, SCP_MOSI 25 GPIO10, SCP_MISO, SCP_SDA 9. 100-pin LQFP with Exposed Pad Package Drawing Figure 22 shows the 100-pin LQFP package with exposed pad for the CS47048, CS47028, and CS47024. 36 CS47024 100-Pin LQFP (Thermal Pad Package) Figure 21. CS47024 Pinout Diagram ...
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Figure 22. 100-Pin LQFP Package Drawing ...
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CS470xx Data Sheet Audio SOC Processor Family 10. Parameter Definitions 10.1 Dynamic Range The ratio of the RMS value of the signal to the RMS sum of all other spectral components over the specified bandwidth. Dynamic Range is a signal-to-noise ...
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... Revision History Revision Date A7 October 16, 2008 Initial Release A8 March 22, 2009 Added CS47028 and CS47024 products to the data sheet. Changed name of data sheet to CS470xx Data Sheet. Added note regarding necessity of power supplies being stable before RESET goes high to A9 April 22, 2009 Updated 5. Updated Standby Power Supply Current: reported as TBD until final measurements are completed ...
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... Described additional support for TDM 8-channel output mode on CS47024: • Removed dagger from the TDM I/O bullet • Straddled “Configurable Serial Audio Inputs/Outputs” row in • Changed cell in “TDM Out” column in • Removed text “On the CS47048 and CS47028...” from PP4 Feb. 10, 2011 Added “Decoder” information to Logic 32-bit core” ...