ltc1407a-1 Linear Technology Corporation, ltc1407a-1 Datasheet - Page 15

• Manufacturer Part Number: ltc1407a-1
• Description: Serial 12-bit, 3msps Simultaneous Sampling Adcs With Shutdown
• Manufacturer: Linear Technology Corporation

APPLICATIO S I FOR ATIO
Board Layout and Bypassing
Wire wrap boards are not recommended for high resolu-
tion and/or high speed A/D converters. To obtain the best
performance from the LTC1407-1/LTC1407A-1, a printed
circuit board with ground plane is required. Layout for the
printed circuit board should ensure that digital and analog
signal lines are separated as much as possible. In particu-
lar, care should be taken not to run any digital track
alongside an analog signal track. If optimum phase match
between the inputs is desired, the length of the four input
wires of the two input channels should be kept matched.
But each pair of input wires to the two input channels
should be kept separated by a ground trace to avoid high
frequency crosstalk between channels.
High quality tantalum and ceramic bypass capacitors should
be used at the V
Diagram on the first page of this data sheet. For optimum
performance, a 10µF surface mount tantalum capacitor
with a 0.1µF ceramic is recommended for the V
pins. Alternatively, 10µF ceramic chip capacitors such as
X5R or X7R may be used. The capacitors must be located
as close to the pins as possible. The traces connecting the
pins and the bypass capacitors must be kept short and
should be made as wide as possible. The V
pacitor returns to GND (Pin 6) and the V
tor returns to the Exposed Pad ground (Pin 11). Care should
1.25V
Figure 6a. The LT1819 Driving the LTC1407A-1 Differentially
MAX
V
P-P
IN
499Ω
R4
499Ω
DD
–
1/2 LT1819
+
R3
–
1/2 LT1819
+
U
and V
U1
U2
–5V
5V
0.1µF
0.1µF
C5
C6
REF
U
pins as shown in the Block
1µF
1µF
C3
C4
R5
1k
R6
1k
W
51Ω
51Ω
R1
R2
1.5V
REF
CM
C1
47pF
C2
47pF
bypass capaci-
DD
DD
bypass ca-
U
+CH0 OR
+CH1
–CH0 OR
–CH1
and V
LTC1407A-1
1407A F06a
REF
be taken to place the 0.1µF V
to Pins 6 and 7 as possible.
Figure 7 shows the recommended system ground connec-
tions. All analog circuitry grounds should be terminated at
Figure 6b. LTC1407-1 6MHz Sine Wave 4096 Point FFT Plot
with the LT1819 Driving the Inputs Differentially
–100
–110
–120
–30
–40
–50
–10
–20
–60
–70
–80
–90
0
0
LTC1407-1/LTC1407A-1
Figure 7. Recommended Layout
185k
FREQUENCY (Hz)
371k
DD
bypass capacitor as close
556k
14031 F06b
741k
15
14071fa
1407-1 F07