ltc1407a-1 Linear Technology Corporation, ltc1407a-1 Datasheet - Page 16

• Manufacturer Part Number: ltc1407a-1
• Description: Serial 12-bit, 3msps Simultaneous Sampling Adcs With Shutdown
• Manufacturer: Linear Technology Corporation

APPLICATIO S I FOR ATIO
LTC1407-1/LTC1407A-1
the LTC1407-1/LTC1407A-1 Exposed Pad. The ground
return from the LTC1407-1/LTC1407A-1 Pin 6 to the
power supply should be low impedance for noise-free
operation. The Exposed Pad of the 10-lead MSE package
is also tied to Pin 6 and the LTC1407-1/LTC1407A-1 GND.
The Exposed Pad should be soldered on the PC board to
reduce ground connection inductance. Digital circuitry
grounds must be connected to the digital supply common.
POWER-DOWN MODES
Upon power-up, the LTC1407-1/LTC1407A-1 are initial-
ized to the active state and are ready for conversion. The
Nap and Sleep mode waveforms show the power-down
modes for the LTC1407-1/LTC1407A-1. The SCK and
CONV inputs control the power-down modes (see Timing
Diagrams). Two rising edges at CONV, without any inter-
vening rising edges at SCK, put the LTC1407-1/LTC1407A-1
in Nap mode and the power drain drops from 14mW to
6mW. The internal reference remains powered in Nap
mode. One or more rising edges at SCK wake up the
LTC1407-1/LTC1407A-1 for service very quickly and CONV
can start an accurate conversion within a clock cycle.
Four rising edges at CONV, without any intervening rising
edges at SCK, put the LTC1407-1/LTC1407A-1 in Sleep
mode and the power drain drops from 14mW to 10µW. To
bring the part out of Sleep mode requires one or more rising
SCK edges followed by a Nap request. Then one or more ris-
ing edges at SCK wake up the LTC1407-1/LTC1407A-1 for
operation. When Nap mode is entered after Sleep mode, the
reference that was shut down in Sleep mode is reactivated.
The internal reference (V
with a 10µF load. Using sleep mode more frequently
compromises the settled accuracy of the internal refer-
ence. Note that for slower conversion rates, the Nap and
Sleep modes can be used for substantial reductions in
power consumption.
DIGITAL INTERFACE
The LTC1407-1/LTC1407A-1 have a 3-wire SPI (Serial
Protocol Interface) interface. The SCK and CONV inputs
and SDO output implement this interface. The SCK and
CONV inputs accept swings from 3V logic and are TTL
16
U
REF
U
) takes 2ms to slew and settle
W
U
compatible, if the logic swing does not exceed V
detailed description of the three serial port signals follows:
Conversion Start Input (CONV)
The rising edge of CONV starts a conversion, but subse-
quent rising edges at CONV are ignored by the LTC1407-1/
LTC1407A-1 until the following 32 SCK rising edges have
occurred. The duty cycle of CONV can be arbitrarily chosen
to be used as a frame sync signal for the processor serial
port. A simple approach to generate CONV is to create a
pulse that is one SCK wide to drive the LTC1407-1/
LTC1407A-1 and then buffer this signal to drive the frame
sync input of the processor serial port. It is good practice
to drive the LTC1407-1/LTC1407A-1 CONV input first to
avoid digital noise interference during the sample-to-hold
transition triggered by CONV at the start of conversion. It
is also good practice to keep the width of the low portion
of the CONV signal greater than 15ns to avoid introducing
glitches in the front end of the ADC just before the sample-
and-hold goes into Hold mode at the rising edge of CONV.
Minimizing Jitter on the CONV Input
In high speed applications where high amplitude sinewaves
above 100kHz are sampled, the CONV signal must have as
little jitter as possible (10ps or less). The square wave
output of a common crystal clock module usually meets
this requirement easily. The challenge is to generate a
CONV signal from this crystal clock without jitter corrup-
tion from other digital circuits in the system. A clock
divider and any gates in the signal path from the crystal
clock to the CONV input should not share the same
integrated circuit with other parts of the system. As shown
in the interface circuit examples, the SCK and CONV inputs
should be driven first, with digital buffers used to drive the
serial port interface. Also note that the master clock in the
DSP may already be corrupted with jitter, even if it comes
directly from the DSP crystal. Another problem with high
speed processor clocks is that they often use a low cost,
low speed crystal (i.e., 10MHz) to generate a fast, but
jittery, phase-locked-loop system clock (i.e., 40MHz). The
jitter in these PLL-generated high speed clocks can be
several nanoseconds. Note that if you choose to use the
frame sync signal generated by the DSP port, this signal
will have the same jitter of the DSP’s master clock.
DD
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