ltc1407a-1 Linear Technology Corporation, ltc1407a-1 Datasheet - Page 17

• Manufacturer Part Number: ltc1407a-1
• Description: Serial 12-bit, 3msps Simultaneous Sampling Adcs With Shutdown
• Manufacturer: Linear Technology Corporation

APPLICATIO S I FOR ATIO
Serial Clock Input (SCK)
The rising edge of SCK advances the conversion process
and also udpates each bit in the SDO data stream. After
CONV rises, the third rising edge of SCK sends out two
sets of 12/14 data bits, with the MSB sent first. A simple
approach is to generate SCK to drive the LTC1407-1/
LTC1407A-1 first and then buffer this signal with the
appropriate number of inverters to drive the serial clock
input of the processor serial port. Use the falling edge of
the clock to latch data from the Serial Data Output (SDO)
into your processor serial port. The 14-bit Serial Data will
be received right justified, in two 16-bit words with 32 or
more clocks per frame sync. It is good practice to drive the
LTC1407-1/LTC1407A-1 SCK input first to avoid digital
noise interference during the internal bit comparison
decision by the internal high speed comparator. Unlike the
CONV input, the SCK input is not sensitive to jitter because
the input signal is already sampled and held constant.
Serial Data Output (SDO)
Upon power-up, the SDO output is automatically reset to
the high impedance state. The SDO output remains in high
impedance until a new conversion is started. SDO sends
out two sets of 12/14 bits in 2’s complement format in the
output data stream after the third rising edge of SCK after
the start of conversion with the rising edge of CONV. The
two 12-/14-bit words are separated by two clock cycles in
high impedance mode. Please note the delay specification
from SCK to a valid SDO. SDO is always guaranteed to be
U
LTC1407A-1
LTC1407-1/
U
CONV
SDO
GND
SCK
V
DD
7
10
9
8
6
W
3V
Figure 8. DSP Serial Interface to TMS320C54x
CONV
CLK
0V TO 3V LOGIC SWING
U
INTERFACELINK
3-WIRE SERIAL
valid by the next rising edge of SCK. The 32-bit output data
stream is compatible with the 16-bit or 32-bit serial port of
most processors.
HARDWARE INTERFACE TO TMS320C54x
The LTC1407-1/LTC1407A-1 are serial output ADCs whose
interface has been designed for high speed buffered serial
ports in fast digital signal processors (DSPs). Figure 8
shows an example of this interface using a TMS320C54X.
The buffered serial port in the TMS320C54x has direct
access to a 2kB segment of memory. The ADC’s serial data
can be collected in two alternating 1kB segments, in real
time, at the full 3Msps conversion rate of the LTC1407-1/
LTC1407A-1. The DSP assembly code sets frame sync
mode at the BFSR pin to accept an external positive going
pulse and the serial clock at the BCLKR pin to accept an
external positive edge clock. Buffers near the LTC1407-1/
LTC1407A-1 may be added to drive long tracks to the DSP
to prevent corruption of the signal to LTC1407-1/
LTC1407A-1. This configuration is adequate to traverse a
typical system board, but source resistors at the buffer
outputs and termination resistors at the DSP, may be
needed to match the characteristic impedance of very long
transmission lines. If you need to terminate the SDO
transmission line, buffer it first with one or two 74ACxx
gates. The TTL threshold inputs of the DSP port respond
properly to the 3V swing used with the LTC1407-1/
LTC1407A-1.
5V
LTC1407-1/LTC1407A-1
B13
B12
V
BFSR
BCLKR
BDR
TMS320C54x
CC
14071 F08
17
14071fa