ltc1407a-1 Linear Technology Corporation, ltc1407a-1 Datasheet - Page 4

• Manufacturer Part Number: ltc1407a-1
• Description: Serial 12-bit, 3msps Simultaneous Sampling Adcs With Shutdown
• Manufacturer: Linear Technology Corporation

POWER REQUIRE E TS
LTC1407-1/LTC1407A-1
range, otherwise specifications are at T
SYMBOL
V
I
PD
TI I G CHARACTERISTICS
range, otherwise specifications are at T
SYMBOL
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground GND.
Note 3: When these pins are taken below GND or above V
clamped by internal diodes. This product can handle input currents greater
than 100mA below GND or greater than V
Note 4: Offset and range specifications apply for a single-ended CH0
CH1
reference.
Note 5: Integral linearity is tested with an external 2.55V reference and is
defined as the deviation of a code from the straight line passing through
the actual endpoints of a transfer curve. The deviation is measured from
the center of quantization band.
Note 6: Guaranteed by design, not subject to test.
Note 7: Recommended operating conditions.
Note 8: The analog input range is defined for the voltage difference
between CH0
CHO
driving CH1
Note 9: The absolute voltage at CH0
within this range.
4
DD
SAMPLE(MAX)
THROUGHPUT
SCK
CONV
1
2
3
4
5
6
7
8
9
10
12
DD
W
+
–
input with CH0
= 1.5V DC while driving CHO
U
+
.
+
PARAMETER
Supply Voltage
Supply Current
Power Dissipation
and CH0
PARAMETER
Maximum Sampling Frequency per Channel
(Conversion Rate)
Minimum Sampling Period (Conversion + Acquisiton Period)
Clock Period
Conversion Time
Minimum Positive or Negative SCLK Pulse Width
CONV to SCK Setup Time
SCK Before CONV
Minimum Positive or Negative CONV Pulse Width
SCK to Sample Mode
CONV to Hold Mode
32nd SCK↑ to CONV↑ Interval (Affects Acquisition Period)
Minimum Delay from SCK to Valid Bits 0 Through 11
SCK to Hi-Z at SDO
Previous SDO Bit Remains Valid After SCK
V
REF
–
Settling Time After Sleep-to-Wake Transition
or CH1
–
or CH1
–
grounded and using the internal 2.5V
+
and CH1
+
+
and with CH1
, CH0
W U
DD
–
–
. Performance is specified with
, CH1
without latchup.
A
A
= 25°C. V
= 25°C. With internal reference, V
+
–
and CH1
= 1.5V DC while
The
CONDITIONS
Active Mode, f
Nap Mode
Sleep Mode (LTC1407)
Sleep Mode (LTC1407A)
Active Mode with SCK in Fixed State (Hi or Lo)
DD
DD
–
, they will be
●
The
must be
= 3V.
denotes the specifications which apply over the full operating temperature
●
denotes the specifications which apply over the full operating temperature
+
SAMPLE
or
= 1.5Msps
CONDITIONS
(Note 16)
(Note 6)
(Note 6)
(Notes 6, 10)
(Note 6)
(Note 6)
(Note 6)
(Notes 6, 11)
(Notes 6, 7, 13)
(Notes 6, 12)
(Notes 6, 12)
(Notes 6, 12)
(Notes 6, 14)
Note 10: If less than 3ns is allowed, the output data will appear one clock
cycle later. It is best for CONV to rise half a clock before SCK, when
running the clock at rated speed.
Note 11: Not the same as aperture delay. Aperture delay (1ns) is the
difference between the 2.2ns delay through the sample-and-hold and the
1.2ns CONV to Hold mode delay.
Note 12: The rising edge of SCK is guaranteed to catch the data coming
out into a storage latch.
Note 13: The time period for acquiring the input signal is started by the
32nd rising clock and it is ended by the rising edge of CONV.
Note 14: The internal reference settles in 2ms after it wakes up from Sleep
mode with one or more cycles at SCK and a 10µF capacitive load.
Note 15: The full power bandwidth is the frequency where the output code
swing drops by 3dB with a 2.5V
Note 16: Maximum clock period guarantees analog performance during
conversion. Output data can be read with an arbitrarily long clock period.
Note 17: The LTC1407A-1 is measured and specified with 14-bit
Resolution (1LSB = 152µV) and the LTC1407-1 is measured and specified
with 12-bit Resolution (1LSB = 610µV).
Note 18: The sampling capacitor at each input accounts for 4.1pF of the
input capacitance.
Note 19: Full-scale sinewaves are fed into the noninverting inputs while
the inverting inputs are kept at 1.5V DC.
DD
= 3V.
●
●
●
●
●
19.6
MIN
P-P
1.5
1.2
32
45
2
3
0
4
4
8
6
2
MIN
input sine wave.
2.7
TYP
34
2
TYP
4.7
1.1
2.0
2.0
12
10000
10000
MAX
667
MAX
3.6
7.0
1.5
15
10
SCLK cycles
UNITS
UNITS
14071fa
MHz
mW
mA
mA
ms
µA
µA
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
V