ltc2493 Linear Technology Corporation, ltc2493 Datasheet - Page 28

• Manufacturer Part Number: ltc2493
• Description: 24-bit 2-/4-channel Delta Sigma Adc With Easy Drive Input Current Cancellation And I2c Interface
• Manufacturer: Linear Technology Corporation

LTC2493
applicaTions inForMaTion
Using the 2X speed mode of the LTC2493 alters the
rejection characteristics around DC and multiples of f
The device bypasses the offset calibration in order to
increase the output rate. The resulting rejection plots are
shown in Figures 26 and 27. 1x type frequency rejection
can be achieved using the 2x mode by performing a run-
ning average of the previoius two conversion results (see
Figure 28).
Output Data Rate
When using its internal oscillator, the LTC2493 produces
up to 15 samples per second (sps) with a notch frequency of
60Hz. The actual output data rate depends upon the length
of the sleep and data output cycles which are controlled
by the user and can be made insignificantly short. When
operating with an external conversion clock (f
to an external oscillator), the LTC2493 output data rate
can be increased. The duration of the conversion cycle is
41036/f
as if the internal oscillator is used.
An increase in f
late into a proportional increase in the maximum output
data rate (up to a maximum of 100sps). The increase in

Figure 26. Input Normal Mode Rejection 2x Speed Mode
EOSC
–100
–120
–20
–40
–60
–80
. If f
0
EOSC
0
EOSC
f
N
over the nominal 307.2kHz will trans-
INPUT SIGNAL FREQUENCY (f
= 307.2kHz, the converter behaves
2f
N
3f
N
4f
N
5f
N
6f
N
N
)
7f
N
2493 F26
8f
O
N
connected
S
.
output rate leads to degradation in offset, full-scale error,
and effective resolution as well as a shift in frequency rejec-
tion. When using the integrated temperature sensor, the
internal oscillator should be used or an external oscillator
f
A change in f
internal notch position. This leads to reduced differential
mode rejection of line frequencies. The common mode
rejection of line frequencies remains unchanged, thus fully
differential input signals with a high degree of symmetry
on both the IN
frequency noise.
An increase in f
input and reference current. External RC networks will
continue to have zero differential input current, but the
time required for complete settling (580ns for f
307.2kHz) is reduced, proportionally.
Once the external oscillator frequency is increased above
1MHz (a more than 3x increase in output rate) the effective-
ness of internal auto calibration circuits begins to degrade.
This results in larger offset errors, full-scale errors, and
decreased resolution, as seen in Figures 29-36.
EOSC
Figure 27. Input Normal Mode Rejection 2x Speed Mode
= 307.2kHz maximum.
–100
–120
–40
–60
–20
–80
0
248
EOSC
+
EOSC
and IN
250
results in a proportional change in the
INPUT SIGNAL FREQUENCY (f
also increases the effective dynamic
252 254 256 258 260 262 264
–
pins will continue to reject line
N
)
2493 F27
EOSC
2493fa
=