ltc4270 Linear Technology Corporation, ltc4270 Datasheet - Page 19

• Manufacturer Part Number: ltc4270
• Description: 12-port Poe/poe+/ltpoe++ Pse Controller
• Manufacturer: Linear Technology Corporation

APPLICATIONS INFORMATION
Reset and the AUTO/MID Pins
The initial LTC4270/LTC4271 configuration depends on the
state of the AUTO and MID pins during reset. Reset occurs
at power-up, or whenever the RESET pin is pulled low or
the global Reset All bit is set. Note that the AUTO pin is
only sampled when a reset occurs. Changing the state of
AUTO or MID after power-up will not properly change the
port behavior of the LTC4270/LTC4271 until a reset occurs.
Although typically used with a host controller, the LTC4270/
LTC4271 can also be used in a standalone mode with no
connection to the serial interface. If there is no host pres-
ent, the AUTO pin should be tied high so that, at reset, all
ports will be configured to operate automatically. Each port
will detect and classify repeatedly until a PD is discovered,
set I
apply power to valid PDs, and remove power when a PD
is disconnected.
Table 3 shows the I
matically set in standalone (AUTO pin) mode, based on
the discovered class.
Table 3. I
CLASS
Class 1
Class 2
Class 3 or 0
Class 4
The automatic setting of I
if the LTC4270/LTC4271 is reset with the AUTO pin high.
If the standalone application is a midspan, the MID pin
should be tied high to enable correct midspan detection
timing.
DETECTION
Detection Overview
To avoid damaging network devices that were not designed
to tolerate DC voltage, a PSE must determine whether the
connected device is a real PD before applying power. The
IEEE specification requires that a valid PD have a common-
CUT
CUT
and I
and I
LIM
LIM
according to the classification results,
Values in Standalone Mode
CUT
and I
112mA
206mA
375mA
638mA
I
CUT
CUT
LIM
and I
values that will be auto-
LIM
values only occurs
425mA
425mA
425mA
850mA
I
LIM
mode resistance of 25k ±5% at any port voltage below 10V.
The PSE must accept resistances that fall between 19k and
26.5k, and it must reject resistances above 33k or below
15k (shaded regions in Figure 11). The PSE may choose to
accept or reject resistances in the undefined areas between
the must-accept and must-reject ranges. In particular, the
PSE must reject standard computer network ports, many
of which have 150Ω common-mode termination resistors
that will be damaged if power is applied to them (the black
region at the left of Figure 11).
4-Point Detection
The LTC4270/LTC4271 uses a 4-point detection method to
discover PDs. False-positive detections are minimized by
checking for signature resistance with both forced-current
and forced-voltage measurements.
Initially, two test currents are forced onto the port (via the
OUTn pin) and the resulting voltages are measured. The
detection circuitry subtracts the two V-I points to determine
the resistive slope while removing offset caused by series
diodes or leakage at the port (see Figure 12). If the forced-
current detection yields a valid signature resistance, two
test voltages are then forced onto the port and the result-
ing currents are measured and subtracted. Both methods
must report valid resistances for the port to report a valid
detection. PD signature resistances between 17k and 29k
(typically) are detected as valid and reported as Detect
Good in the corresponding Port Status register. Values
outside this range, including open and short circuits, are
also reported. If the port measures less than 1V at the
first forced-current test, the detection cycle will abort and
Short Circuit will be reported. Table 4 shows the possible
detection results.
RESISTANCE
Figure 11. IEEE 802.3af Signature Resistance Ranges
PSE
PD
0Ω
150Ω (NIC)
LTC4270/LTC4271
10k
15k
20k
19k
23.75k
26.25k
26.5k
30k
33k
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