ltc4270 Linear Technology Corporation, ltc4270 Datasheet - Page 25

• Manufacturer Part Number: ltc4270
• Description: 12-port Poe/poe+/ltpoe++ Pse Controller
• Manufacturer: Linear Technology Corporation

APPLICATIONS INFORMATION
SERIAL DIGITAL INTERFACE
Overview
The LTC4270/LTC4271 communicates with the host us-
ing a standard SMBus/I
LTC4271 is a slave-only device, and communicates with
the host master using the standard SMBus protocols.
Interrupts are signaled to the host via the INT pin. The
Timing Diagrams (Figures 5 through 9) show typical
communication waveforms and their timing relationships.
More information about the SMBus data protocols can be
found at www.smbus.org.
The LTC4270/LTC4271 requires both the V
ply rails to be present for the serial interface to function.
Bus Addressing
The LTC4270/LTC4271’s primary 7-bit serial bus address
is A
lower four bits set by the AD3-AD0 pins; this allows up
to 10 LTC4270/LTC4271s, on a single bus. Ten LTC4270/
LTC4271 are equivalent to 30 quad PSEs or 120 ports. All
LTC4270/LTC4271s also respond to the broadcast address
0110000b, allowing the host to write the same command
(typically configuration commands) to multiple LTC4270/
LTC4271s in a single transaction. If the LTC4270/LTC4271
is asserting the INT pin, it will also respond to the alert
response address (0001100b) per the SMBus specification.
Each LTC4270/LTC4271 is logically composed of three
quads of four ports each. Each quad occupies separate,
contiguous I
address of the base quad while the remaining quads are
consecutively numbered. I
x10xxxxb range are considered illegal and will not respond.
Each internal quad is independent of the other quads, with
the exception of writes to the Chip Reset, MSD Inversion
and General Purpose Input Output registers. These registers
are global in nature and will affect all quads.
6
10A
3
A
2
A
2
1
C addresses. The AD6, AD3-0 pins set the
A
0
b, with bit 6 controlled by AD6 and the
2
C 2-wire interface. The LTC4270/
2
C addresses outside of the
DD
and V
EE
sup-
Interrupts and SMBAlert
Most LTC4270/LTC4271 port events can be configured
to trigger an interrupt, asserting the INT pin and alerting
the host to the event. This removes the need for the host
to poll the LTC4270/LTC4271, minimizing serial bus traf-
fic and conserving host CPU cycles. Multiple LTC4270/
LTC4271s can share a common INT line, with the host
using the SMBAlert protocol (ARA) to determine which
LTC4270/LTC4271 caused an interrupt.
Register Description
For information on serial bus usage and device configura-
tion and status, refer to the LTC4271 Software Program-
ming documentation.
ISOLATION REQUIREMENTS
IEEE 802.3 Ethernet specifications require that network
segments (including PoE circuitry) be electrically isolated
from the chassis ground of each network interface device.
However, network segments are not required to be isolated
from each other, provided that the segments are connected
to devices residing within a single building on a single
power distribution system.
SDA
SCL
Figure 14. Example I
AD0
AD1
AD2
AD3
AD6
SCL
SDAIN
SDAOUT
LTC4271
LTC4270/LTC4271
I
2
C ADDRESS
0100000
0100001
0100010
2
3.3V
C Bus Addressing
AD0
AD1
AD2
AD3
AD6
SCL
SDAIN
SDAOUT
LTC4271
42701 F15
I
2
C ADDRESS
0100111
0101000
0101001
25
42701f