rm5261a pmc-sierra, rm5261a Datasheet - Page 15

• Manufacturer Part Number: rm5261a
• Description: Rm5261a Tm Microprocessor With 64-bit System Bus
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2002240, Issue 4
3.12 System Control Co-Processor Registers
3.13 Virtual to Physical Address Mapping
The RM5261A incorporates all system control co-processor (CP0) registers on-chip. These
registers provide the path through which the virtual memory system’s page mapping is examined
and modified, exceptions are handled, and operating modes are controlled (kernel vs. user mode,
interrupts enabled or disabled, cache features). In addition, the RM5261A includes registers to
implement a real-time cycle counting facility to aid in cache diagnostic testing and to assist in data
error detection.
Figure 4 shows the CP0 registers.
Figure 4 CP0 Registers
The RM5261A provides three modes of virtual addressing:
•
•
•
This mechanism allows system software to provide a secure environment for user processes. Bits
in the CP0 register Status determine which virtual addressing mode is used. In the user mode, the
RM5261A provides a single, uniform virtual address space of 1 TB (2 GB in 32-bit mode).
When operating in the kernel mode, four distinct virtual address spaces, totalling over 2.5 TB (4
GB in 32-bit mode), are simultaneously available and are differentiated by the high-order bits of
the virtual address.
* Register number
user mode
kernel mode
supervisor mode
LLAddr
17*
47
0
PageMask
EntryHi
TagLo
10*
28*
(entries protected
5*
from TLBWR)
TLB
Used for memory
RM5261A™ Microprocessor with 64-Bit System Bus Data Sheet
management
EntryLo0
EntryLo1
2*
3*
TagHi
29*
Random
Config
Wired
Index
PRId
15*
16*
0*
1*
6*
Context
Status
Count
ECC
EPC
12*
14*
26*
4*
9*
Used for exception
BadVAddr
ErrorEPC
Compare
XContext
CacheErr
Cause
processing
13*
20*
27*
30*
11*
8*
Released
16