rm5261a pmc-sierra, rm5261a Datasheet - Page 22

• Manufacturer Part Number: rm5261a
• Description: Rm5261a Tm Microprocessor With 64-bit System Bus
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2002240, Issue 4
3.25 Non-overlapping System Interface
transaction. The RM5261A samples these signals before deasserting the address on read and write
requests.
ExtRqst* and Release* are used to transfer control of the SysAD and SysCmd buses from the
processor to an external device. When an external device needs to control the interface, it asserts
ExtRqst*. The RM5261A responds by asserting Release* to release the system interface to slave
state.
ValidOut* and ValidIn* are used by the RM5261A and the external device respectively to
indicate that there is a valid address, a command, or data on the SysAD and SysCmd buses. The
RM5261A asserts ValidOut* when it is driving these buses with a valid address, a command, or
data, and the external device drives ValidIn* when it has control of the buses and is driving a valid
address, a command, or data.
The RM5261A implements a non-overlapping system interface, meaning that only one processor
request may be outstanding at a time and that the request must be serviced by an external device
before the RM5261A issues another request. The RM5261A can issue read and write requests to
an external device, whereas an external device can issue null and write requests to the RM5261A.
For processor reads the RM5261A asserts ValidOut* and simultaneously drives the address and
read command on the SysAD and SysCmd buses respectively. If the system interface has RdRdy*
asserted, then the processor tristates its drivers and releases the system interface to the slave state
by asserting Release*. The external device can then begin sending data to the RM5261A.
Figure 7 shows a processor block read request and the external agent read response. The read
latency is 4 cycles (ValidOut* to ValidIn*), and the response data pattern is DDDD, indicating
that data can be transferred on every clock with no wait states in-betwee n.
Figure 7 Processor Block Read
SysAD
SysClock
SysCmd
ValidOut*
ValidIn*
RdRdy*
WrRdy*
Release*
Read
Addr
RM5261A™ Microprocessor with 64-Bit System Bus Data Sheet
NData
Data0
NData
Data1
NData
Data2
NEOD
Data3
Released
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