s29al008d Meet Spansion Inc., s29al008d Datasheet - Page 16

• Manufacturer Part Number: s29al008d
• Description: 8 Megabit 1 M X 8-bit/512 K X 16-bit Cmos 3.0 Volt-only Boot Sector Flash Memory
• Manufacturer: Meet Spansion Inc.

7.7
7.8
16
RESET#: Hardware Reset Pin
Output Disable Mode
The RESET# pin provides a hardware method of resetting the device to reading array data. When the
RESET# pin is driven low for at least a period of t
progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse.
The device also resets the internal state machine to reading array data. The operation that was interrupted
should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held at V
draws CMOS standby current (I
greater.
The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firmware from the Flash memory.
If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a 0 (busy) until the
internal reset operation is complete, which requires a time of t
system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is
asserted when a program or erase operation is not executing (RY/BY# pin is 1), the reset operation is
completed within a time of t
RESET# pin returns to V
Refer to
diagram.
When the OE# input is at V
impedance state.
Note
Address range is A18:A-1 in byte mode and A18:A0 in word mode. See
Sector
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
AC Characteristics on page 36
A18
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
A17
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
A16
IH
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
1
Table 7.2 S29AL008D Top Boot Block Sector Addresses
.
READY
IH
, output from the device is disabled. The output pins are placed in the high
CC4
A15
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
(not during Embedded Algorithms). The system can read data t
). If RESET# is held at V
A14
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
1
1
S29AL008D
for RESET# parameters and to
D a t a
A13
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
RP
, the device immediately terminates any operation in
A12
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
S h e e t
Word/Byte Configuration on page
IL
Sector Size
(Kbytes/
Kwords)
but not within V
READY
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
32/16
16/8
8/4
8/4
(during Embedded Algorithms). The
S29AL008D_00_A10 November 27, 2007
Figure 15.2 on page 37
A0000h–AFFFFh
B0000h–BFFFFh
C0000h–CFFFFh
D0000h–DFFFFh
E0000h–EFFFFh
FA000h–FBFFFh
FC000h–FFFFFh
F0000h–F7FFFh
F8000h–F9FFFh
Address Range
00000h–0FFFFh
10000h–1FFFFh
20000h–2FFFFh
30000h–3FFFFh
40000h–4FFFFh
50000h–5FFFFh
60000h–6FFFFh
70000h–7FFFFh
80000h–8FFFFh
90000h–9FFFFh
SS
Address Range (in hexadecimal)
±0.3 V, the standby current is
(x8)
14.
SS
±0.3 V, the device
7C000h–7CFFFh
7D000h–7DFFFh
78000h–7BFFFh
7E000h–7FFFFh
00000h–07FFFh
08000h–0FFFFh
10000h–17FFFh
18000h–1FFFFh
20000h–27FFFh
28000h–2FFFFh
30000h–37FFFh
38000h–3FFFFh
40000h–47FFFh
48000h–4FFFFh
50000h–57FFFh
58000h–5FFFFh
60000h–67FFFh
68000h–6FFFFh
70000h–77FFFh
Address Range
for the timing
RH
(x16)
after the