tsa5520 NXP Semiconductors, tsa5520 Datasheet - Page 7

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tsa5520

Manufacturer Part Number
tsa5520
Description
1.3 Ghz Universal Bus-controlled Tv Synthesizer
Manufacturer
NXP Semiconductors
Datasheet

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Table 2 Bus format selection
Table 3 I
Table 4 Description of Table 3
Table 5 I
1996 Oct 10
Address Byte (ADB)
Divider Byte 1 (DB1)
Divider Byte 2 (DB2)
Control Byte (CB)
Band switch Byte (BB)
A
MA1 and MA0
N14 to N0
CP
T2 to T0
RSA and RSB
OS
BS4 to BS1
X
0 to 0.1V
Always valid
0.4V
0.9V
1.3 GHz universal bus-controlled
TV synthesizer
VOLTAGE APPLIED TO THE
CE INPUT (SW = LOW)
CC1
CC1
SYMBOL
BYTE
to 0.6V
to V
PIN
CC1
13
14
15
2
2
11
C-bus data format
C-bus address selection
CC1
CC1
acknowledge
programmable address bits (see Table 5)
programmable divider bits; N = N14
charge-pump current; CP = 0 = 60 A; CP = 1 = 280 A
test bits (see Table 6); for normal operation T2 = 0, T1 = 0 and T0 = 1
reference divider ratio select bits (see Table 7)
tuning amplifier control bit; for normal operation OS = 0 and tuning voltage is ON;
when OS = 1 tuning voltage is OFF (high impedance)
PNP band switch buffers control bits; when BS
when BS
don’t care
MSB
N7
X
1
0
1
NAME
SDA
SCL
SW
CE
n
N14
CP
N6
= 1 buffer n is ON
X
1
MA1
0
0
1
1
N13
N5
T2
X
0
MA0
0
1
0
1
N12
DATA BYTE
N4
T1
X
0
7
3-WIRE BUS MODE
BS4
N11
chip enable input
N3
T0
0
open or HIGH
2
DESCRIPTION
clock input
14
data input
+ N13
MA1
RSA
N10
BS3
N2
n
= 0 buffer n is OFF;
2
13
MA0
RSB
BS2
N9
N1
+ ... + N1
TSA5520; TSA5521
LSB
BS1
OS
N8
N0
0
2 + N0
address selection input
SLAVE ANSWER
SDA input/output
I
Product specification
2
C BUS MODE
SCL input
LOW
A
A
A
A
A

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