mt352cggp2q Zarlink Semiconductor, mt352cggp2q Datasheet

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mt352cggp2q

Manufacturer Part Number
mt352cggp2q
Description
Cofdm Demodulator
Manufacturer
Zarlink Semiconductor
Datasheet
Features
Applications
Nordig II and ETSI 300 744 compliant
Superior Single Frequency Network performance
Unique active Impulse-Noise filtering
Single SAW operation
Automatic co-channel and adjacent-channel
interference suppression
Clock generation from single low-cost 20.48 MHz
crystal or external 4 or 27 MHz clock
IF sampling at 4.57, 36.17 or 43.5 MHz from a
single crystal frequency
Channel bandwidth of 6, 7 & 8 MHz
Blind acquisition capability (including 2 K / 8 K
mode detect)
Automatic spectral inversion detection
Fast auto-scan and acquisition technology
Very low software overhead
Dual AGC control option
Access to channel SNR, pre- and post-Viterbi bit
error rates
Compact 64 pin LQFP
Less than 0.22 W power consumption
Standby and sleep options
Set-top boxes
Integrated digital televisions
Personal video recorders
Terrestrial PC reception
Mobile and portable applications
RF in
Secondary
2-wire bus
ADC
AGC
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Tuner control
conversion &
Suppression
Interpolator
Baseband
Impulse
Copyright 2003-2005, Zarlink Semiconductor Inc. All Rights Reserved.
IF to
Recovery
Carrier &
Figure 1 - Block Diagram
Symbol,
Zarlink Semiconductor Inc.
Timing
FFT
1
Zarlink evaluation kits include application board, TNIM
and supporting software based on industry standard
operating systems. Device drivers are also available
enabling rapid product development and reduction in
time to market.
Description
MT352
Orthogonal Frequency Division Multiplex (COFDM)
television demodulator that is both Nordig II and DVB
(as defined in ETS 300 744 specification) compliant. It
can be used in
8 MHz channels and is capable of addressing all
modes of transmission.
The device includes a high performance 10-bit A/D
converter capable of accepting direct IF at 36.17 or
43.75 MHz.
frequencies in 6,7 or 8 MHz OFDM channels can be
generated
Alternatively, there is provision to replace this crystal
with a 4 or 27 MHz external clock input.
Processor
Channel
Pilot &
MT352/CG/GP1N
MT352/CG/GP1Q
MT352/CG/GP2Q
MT352/CG/GP2N
is
from
a
Sampling rates required for both these
Control
engine
Ordering Information
superior
De-interleaver
either 2 K or 8 K modes with 6, 7 or
Symbol & Bit
* Pb Free Matte Tin
& Demapper
a
0
o
COFDM Demodulator
C to +70
64 Pin LQFP
64 Pin LQFP
64 Pin LQFP* Trays
64 Pin LQFP* Tape & Reel
single
third
2-wire bus
o
Primary
C
20.48 MHz
generation
FEC
Trays
Tape & Reel
Data Sheet
February 2005
MPEG
MT352
TS
crystal.
Coded

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mt352cggp2q Summary of contents

Page 1

... Interpolator AGC Impulse Suppression Secondary 2-wire bus Tuner control Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003-2005, Zarlink Semiconductor Inc. All Rights Reserved. Ordering Information MT352/CG/GP1N MT352/CG/GP1Q MT352/CG/GP2Q MT352/CG/GP2N * Pb Free Matte Tin ...

Page 2

... The frequency capture range is sufficient to compensate for the combined offset introduced by the tuner and broadcaster. The device is packaged pin LQFP and consumes less than 220 mW of power. MT352 MT352 CG ∆ YYWW*W • Pin 1 Corner Figure 2 - Package Outline 2 Zarlink Semiconductor Inc. Data Sheet ...

Page 3

... Primary AGC O Secondary AGC I/O General purpose I/O I/O Device reset I CMOS Crystal oscillator mode I CMOS PLL analogue test O positive input I negative input I 3 Zarlink Semiconductor Inc. Data Sheet Type V mA 3·3 1 3·3 1 3·3 1 3·3 1 3·3 1 3·3 3· ...

Page 4

... AVDD 29, 32 AGND 33 DVDD 34 DGND MT352 Description I/O PLL supply S S Core logic power S I/O ring power S Core and I/O ground S ADC analog supply S S ADC digital supply Zarlink Semiconductor Inc. Data Sheet Type V mA 1·8 0 1·8 3·3 0 1·8 0 1·8 0 ...

Page 5

... Data Output Header Format 3.3.2 MPEG data output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3.3 MPEG Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3.3.1 MOCLKINV = 3.3.3.2 MOCLKINV = 4.0 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.1 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.3 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.4 Crystal Specification and External Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.0 Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 MT352 Table of Contents 5 Zarlink Semiconductor Inc. Data Sheet ...

Page 6

... Figure 6 - Primary 2-Wire Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 7 - DVB Transport Packet Header Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 8 - MPEG Output Data Waveforms Figure 9 - MPEG Timing - MOCLKINV = Figure 10 - MPEG Timing - MOCLKINV = Figure 11 - Crystal Oscillator Circuit Figure 12 - Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 MT352 List of Figures 6 Zarlink Semiconductor Inc. Data Sheet ...

Page 7

... Table 1 - Programmable Address Details for 2-Wire Bus in TNIM Evaluation Application Table 2 - Timing of 2-Wire Bus Table 3 - MOCLKINV = Table 4 - MDOSWAP = Table 5 - MDOSWAP = MT352 List of Tables 7 Zarlink Semiconductor Inc. Data Sheet ...

Page 8

... The controller facilitates the automated search of all parameters or any sub-set of parameters of the received signal. It can also be used to scan any defined frequency range searching for OFDM channels. This MT352 Figure 3 - OFDM Demodulator Diagram Figure 4 - FEC Block Diagram 8 Zarlink Semiconductor Inc. Data Sheet ...

Page 9

... A correction for spectral inversion is implemented during this conversion process. Note also that the MT352 has control mechanisms to search automatically for an unknown spectral inversion status. MT352 9 Zarlink Semiconductor Inc. Data Sheet ...

Page 10

... This module also generates dynamic channel state information (CSI) for every carrier in every symbol. 1.11 Impulse Filtering MT352 contains several mechanisms to reduce the impact of impulse noise on system performance. MT352 10 Zarlink Semiconductor Inc. Data Sheet ...

Page 11

... It may also detect frames with more than eight byte errors. In addition to efficiently performing this decoding function, the Reed-Solomon decoder in MT352 keeps a count of the number of bit errors corrected over a programmable period and the number of uncorrectable blocks. This information can be used to compute the post-Viterbi BER. MT352 11 Zarlink Semiconductor Inc. Data Sheet ...

Page 12

... The MT352 interfaces to other parts of a terrestrial receiver system can be partitioned into three groups: the host controller, the tuner and the MPEG decoder. One other pin, the Status output, is multi-functional and can directly MT352 Figure 5 - Primary Interfaces 12 Zarlink Semiconductor Inc. Data Sheet ...

Page 13

... The MT352 has a General Purpose Port that can be configured to provide a secondary 2-wire bus. Master control mode is selected by a single register control bit. The allocation of the pins is: GPP0 pin 35 = CLK2, GPP1 pin 36 = DATA2. MT352 ADDR[5] ADDR[4] ADDR[3] SADD[4] SADD[3] SADD[2] VSS VDD VDD 13 Zarlink Semiconductor Inc. Data Sheet ADDR[2] ADDR[1] SADD[1] SADD[0] VDD VDD ...

Page 14

... RADD W A RADD A DATA (n) (reg DATA A DATA (reg 0) (reg DEVICE R (n) ADDRESS Figure 6 - Primary 2-Wire Bus Timing 14 Zarlink Semiconductor Inc. Data Sheet W Write (=0) R Read (= 1) NA NOT Acknowledge Register Address A DATA A P (reg n+1) A DATA NA P (reg 2) A DATA A DATA ...

Page 15

... HD;STA t LOW t HIGH t SU;STA t HD;DAT t SU;DAT SU;STO Table 2 - Timing of 2-Wire Bus Figure 7 - DVB Transport Packet Header Byte 15 Zarlink Semiconductor Inc. Data Sheet Value Symbol Min. Max. 0 450 200 200 1300 600 200 100 100 note 1 20 200 Unit kHz ...

Page 16

... MPEG Output Timing Maximum delay conditions: VDD = 3.0 V, CVDD = 1.62 V, Tamb = 70 Minimum delay conditions: VDD = 3.6 V, CVDD = 1.98 V, Tamb = 0 MOCLK frequency = 61.44 MHz. MT352 Figure 8 - MPEG Output Data Waveforms o C, Output load = Output load = Zarlink Semiconductor Inc. Data Sheet ...

Page 17

... Parameter Data output delay t D Setup Time t SU Hold Time t H MT352 Minimum Delay Conditions 0 Table 3 - MOCLKINV = 1 Figure 9 - MPEG Timing - MOCLKINV = 1 Maximum Delay Conditions 1.5 ns Table 4 - MDOSWAP = 0 17 Zarlink Semiconductor Inc. Data Sheet Minimum Delay Conditions 0 0.5 ns ...

Page 18

... This improves the hold time: MDOSWAP = 1 Parameter Data output delay t D Setup Time t SU Hold Time t H MT352 Maximum Delay Conditions Table 5 - MDOSWAP = 1 Figure 10 - MPEG Timing - MOCLKINV = 0 18 Zarlink Semiconductor Inc. Data Sheet Minimum Delay Conditions 0 1.2 ns ...

Page 19

... IDD P core IDD C XTI 16·00 fCLK 0 Symbol VDD -0.3 CVDD -0.3 VI -0.3 VI -0.3 VO -0.3 VO -0.3 TSTG -55 TOP Zarlink Semiconductor Inc. Data Sheet Typ. Max. Units 3·3 3·6 V 1·8 1· 120 mA 20·48 25·00 MHz 450 kHz ° kΩ Min. Max. Unit +3 ...

Page 20

... STATUS, BKERR GPP(3:0), DATA1, AGC1, AGC2 IRQ MICLK, SADD(4:0), VIH SLEEP, OSC- MODE GPP(3:0), CLK1, VIH DATA1, RESET All inputs VIL SLEEP, SMTEST, MICLK, CLK1, OSCMODE SADD(4:0), DATA1, GPP(3:0) 20 Zarlink Semiconductor Inc. Data Sheet Min. Typ. Max. Unit 3.0 3.3 3.6 V 1.62 1.8 1.98 V 120 mA 200 µA 2 ...

Page 21

... Parallel resonant fundamental frequency (preferred) Tolerance over operating temperature range Tolerance overall Typical load capacitance Drive level Equivalent series resistance C1 MT352 20.4800 MHz ± 25 ppm ± 50 ppm 27 pF 0.4 mW max. <50 Ω XTI XTO XT1 C2 Figure 11 - Crystal Oscillator Circuit 21 Zarlink Semiconductor Inc. Data Sheet OSCMODE ...

Page 22

... Application Circuit MT352 Figure 12 - Typical Application Circuit 22 Zarlink Semiconductor Inc. Data Sheet ...

Page 23

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Page 24

... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...

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