mt352cggp2q Zarlink Semiconductor, mt352cggp2q Datasheet - Page 15

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mt352cggp2q

Manufacturer Part Number
mt352cggp2q
Description
Cofdm Demodulator
Manufacturer
Zarlink Semiconductor
Datasheet
Note 1. The rise time depends on the external bus pull up resistor. Loading prevents full speed operation.
3.3
3.3.1
CLK clock frequency (Primary)
Bus free time between a STOP and START condition
Hold time (repeated) START condition
LOW period of CLK clock
HIGH period of CLK clock
Set-up time for a repeated START condition
Data hold time (when input)
Data set-up time
Rise time of both CLK and DATA signal.
Fall time of both CLK and DATA signals, (100 pF to ground)
Set-up time for a STOP condition
MPEG
Data Output Header Format
Parameter
Figure 7 - DVB Transport Packet Header Byte
Table 2 - Timing of 2-Wire Bus
Zarlink Semiconductor Inc.
MT352
15
f
t
t
t
t
t
t
t
t
t
t
CLK
BUFF
HD;STA
LOW
HIGH
SU;STA
HD;DAT
SU;DAT
R
F
SU;STO
Symbol
0
200
200
1300
600
200
100
100
20
200
Min.
Value
450
note 1
Max.
Data Sheet
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit

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