mt352cggp2q Zarlink Semiconductor, mt352cggp2q Datasheet - Page 13

• Manufacturer Part Number: mt352cggp2q
• Description: Cofdm Demodulator
• Manufacturer: Zarlink Semiconductor

drive a LED to show the status of a range of different internal lock flags. Alternatively, it can drive an audio
transducer to give an audio frequency that is dependent upon the error rate of the received signal.
This feature can be used for faster installation of a system where the aerial may need to be adjusted, as signal
strength is not the best guide for the optimum aerial position for COFDM reception.
3.1
3.2
The primary 2-wire bus serial interface uses pins:
•
•
The 2-wire bus address is determined by applying VDD or VSS to the SADD[4:0] pins.
In the current TNIM evaluation application, the 2-wire bus address is 0001 111 R/ W with the pins connected as
follows:
When the MT352 is powered up, the RESET pin 28 should be held low for at least 50ms after VDD has reached
normal operation levels. As the RESET pin goes high, the logic levels on SADD[4:0] are latched as the 2-wire bus
address. ADDR[0] is the R/ W bit.
The circuit works as a slave transmitter with the lsb set high or as a slave receiver with the lsb set low. In receive
mode, the first data byte is written to the RADD virtual register, which forms the register sub-address. The RADD
register takes an 8-bit value that determines which of 256 possible register addresses is written to by the following
byte. Not all addresses are valid and many are reserved registers that must not be changed from their default
values. Multiple byte reads or writes will auto-increment the value in RADD, but care should be taken not to access
the reserved registers accidentally.
Following a valid chip address, the 2-wire bus STOP command resets the RADD register to 00. If the chip address
is not recognized, the MT352 will ignore all activity until a valid chip address is received. The 2-wire bus START
command does NOT reset the RADD register to 00. This allows a combined 2-wire bus message, to point to a
particular read register with a write command, followed immediately with a read data command. If required, this
could next be followed with a write command to continue from the latest address. RADD would not be sent in this
case. Finally, a STOP command should be sent to free the bus.
When the 2-wire bus is addressed (after a recognized STOP command) with the read bit set, the first byte read out
is the contents of register 00.
3.2.1
The MT352 has a General Purpose Port that can be configured to provide a secondary 2-wire bus. Master control
mode is selected by a single register control bit.
The allocation of the pins is: GPP0 pin 35 = CLK2, GPP1 pin 36 = DATA2.
DATA1 (pin 5) serial data, the most significant bit is sent first.
CLK1 (pin 4) serial clock.
2-Wire Bus
Host
Tuner
Table 1 - Programmable Address Details for 2-Wire Bus in TNIM Evaluation Application
ADDR[7]
Not programmable
VSS
ADDR[6]
VSS
ADDR[5]
SADD[4]
VSS
Zarlink Semiconductor Inc.
MT352
ADDR[4]
SADD[3]
VDD
13
ADDR[3]
SADD[2]
VDD
ADDR[2]
SADD[1]
VDD
ADDR[1]
SADD[0]
VDD
Data Sheet