mt48lc2m32b2 Micron Semiconductor Products, mt48lc2m32b2 Datasheet - Page 40

• Manufacturer Part Number: mt48lc2m32b2
• Description: Synchronous Dram
• Manufacturer: Micron Semiconductor Products

PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5
64MSDRAMx32_2.fm - Rev. J 12/08 EN
10. READs or WRITEs listed in the Command (Action) column include READs or WRITEs with
11. Does not affect the state of the bank and acts as a NOP to that bank.
5. The following states must not be interrupted by any executable command; COMMAND
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle.
8. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid
9. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regard-
INHIBIT or NOP commands must be applied on each positive clock edge during these states.
Refreshing:
Accessing mode
register:
Precharging all:
state for precharging.
less of bank.
auto precharge enabled and READs or WRITEs with auto precharge disabled.
Starts with registration of an AUTO REFRESH command and ends
when
idle state.
Starts with registration of a LOAD MODE REGISTER command and
ends when
be in the all banks idle state.
Starts with registration of a PRECHARGE ALL command and ends
when
40
t
t
RC is met. After
RP is met. After
t
MRD has been met. After
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
t
RC is met, the SDRAM will be in the all banks
RP is met, all banks will be in the idle state.
t
MRD is met, the SDRAM will
©2001 Micron Technology, Inc. All rights reserved.
64Mb: x32 SDRAM
Commands