mt4lc4m16r6 Micron Semiconductor Products, mt4lc4m16r6 Datasheet - Page 4

• Manufacturer Part Number: mt4lc4m16r6
• Description: 4 Meg X 16 Edo Dram
• Manufacturer: Micron Semiconductor Products

DRAM ACCESS (continued)
the upper byte (DQ8-DQ15). General byte and word
access timing is shown in Figures 1 and 2.
logic LOW on WE# dictates write mode. During a
WRITE cycle, data-in (D) is latched by the falling edge
of WE or CAS# (CASL# or CASH#), whichever occurs
last. An EARLY WRITE occurs when WE is taken LOW
prior to either CAS# falling. A LATE WRITE or READ-
MODIFY-WRITE occurs when WE falls after CAS# (CASL#
or CASH#) is taken LOW. During EARLY WRITE cycles,
the data outputs (Q) will remain High-Z, regardless of
the state of OE#. During LATE WRITE or READ-MODIFY-
WRITE cycles, OE# must be taken HIGH to disable the
data outputs prior to applying input data. If a LATE
WRITE or READ-MODIFY-WRITE is attempted while
keeping OE# LOW, no write will occur, and the data
outputs will drive read data from the accessed location.
mode of operation if both bytes are active. A CAS#
precharge must be satisfied prior to changing modes of
operation between the upper and lower bytes. For
example, an EARLY WRITE on one byte and a LATE
4 Meg x 16 EDO DRAM
D29_2.p65 – Rev. 5/00
A logic HIGH on WE# dictates read mode, while a
Additionally, both bytes must always be of the same
LOWER BYTE
UPPER BYTE
(DQ8-DQ15)
(DQ0-DQ7)
OF WORD
OF WORD
CASH#
CASL#
RAS#
WE#
STORED
Z = High-Z
DATA
WORD and BYTE READ Example
1
1
0
1
1
1
1
1
0
1
0
1
0
0
0
0
OUTPUT
DATA
1
1
0
1
1
1
1
1
Z
Z
Z
Z
Z
Z
Z
Z
ADDRESS 0
WORD READ
OUTPUT
DATA
1
1
0
1
1
1
1
1
0
1
0
1
0
0
0
0
Figure 2
STORED
DATA
4
1
1
0
1
1
1
1
1
0
1
0
1
0
0
0
0
WRITE on the other byte are not allowed during the
same cycle. However, an EARLY WRITE on one byte and
a LATE WRITE on the other byte, after a CAS# precharge
has been satisfied, are permissible.
EDO PAGE MODE
output buffers off (High-Z) with the rising edge of
CAS#. If CAS# went HIGH and OE# was LOW (active),
the output buffers would be disabled. The 64Mb EDO
DRAM offers an accelerated page mode cycle by elimi-
nating output disable from CAS# HIGH. This option is
called EDO, and it allows CAS# precharge time (
occur without the output data going invalid (see READ
and EDO-PAGE-MODE READ waveforms).
MODE READ, except data is held valid after CAS# goes
HIGH, as long as RAS# and OE# are held LOW and WE#
is held HIGH. OE# can be brought LOW or HIGH while
CAS# and RAS# are LOW, and the DQs will transition
between valid data and High-Z. Using OE#, there are
STORED
DATA
0
1
0
1
0
0
0
0
1
1
0
1
1
1
1
1
DRAM READ cycles have traditionally turned the
EDO operates like any DRAM READ or FAST-PAGE-
Micron Technology, Inc., reserves the right to change products or specifications without notice.
LOWER BYTE READ
OUTPUT
DATA
ADDRESS 1
1
1
0
1
1
1
1
1
Z
Z
Z
Z
Z
Z
Z
Z
OUTPUT
DATA
1
1
0
1
1
1
1
1
Z
Z
Z
Z
Z
Z
Z
Z
STORED
DATA
1
1
0
1
1
1
1
1
0
1
0
1
0
0
0
0
4 MEG x 16
EDO DRAM
©2000, Micron Technology, Inc.
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CP) to