mt45w4mw16b Micron Semiconductor Products, mt45w4mw16b Datasheet - Page 10

• Manufacturer Part Number: mt45w4mw16b
• Description: Async/page/burst Cellularramtm 1.0 Memory
• Manufacturer: Micron Semiconductor Products

Figure 5:
Figure 6:
Page Mode READ Operation
PDF: 09005aef80be1fbd/Source: 09005aef80be2036
Burst CellularRAM_2.fm - Rev. G 10/05 EN
READ Operation (ADV = LOW)
WRITE Operation (ADV = LOW)
Note:
ADDRESS
Page mode is a performance-enhancing extension to the legacy asynchronous READ
operation. In page-mode-capable products, an initial asynchronous read access is per-
formed, then adjacent addresses can be read quickly by simply changing the low-order
address. Addresses A[3:0] are used to determine the members of the 16-address Cellular-
RAM page. Any change in addresses A[4] or higher will initiate a new
Figure 7 shows the timing for a page mode access. Page mode takes advantage of the fact
that adjacent addresses can be read in a shorter period of time than random addresses.
WRITE operations do not include comparable page mode functionality.
During asynchronous page mode operation, the CLK input must be static (HIGH or LOW
– no transitions). CE# must be driven HIGH upon completion of a page mode access.
WAIT will be driven while the device is enabled and its state should be ignored. Page
mode is enabled by setting RCR[7] to HIGH. ADV must be driven LOW during all page
mode read accesses.
ADDRESS
LB#/UB#
LB#/UB#
DATA
DATA
WE#
WE#
OE#
OE#
CE#
ADV must remain LOW for page mode operation.
CE#
64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
t WC = WRITE Cycle Time
t RC = READ Cycle Time
ADDRESS VALID
ADDRESS VALID
< t CEM
10
DATA VALID
DATA VALID
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DON’T CARE
DON’T CARE
Bus Operating Modes
©2003 Micron Technology, Inc. All rights reserved.
t
AA access time.