mt45w1mw16bdgb Micron Semiconductor Products, mt45w1mw16bdgb Datasheet - Page 11

• Manufacturer Part Number: mt45w1mw16bdgb
• Description: 16mb 1 Meg X 16 Async/page/burst Cellularram 1.0 Memory
• Manufacturer: Micron Semiconductor Products

Figure 5:
Figure 6:
Page Mode READ Operation
PDF: 09005aef81cb58ed/Source: 09005aef81c7a667
16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN
READ Operation (ADV = LOW)
WRITE Operation (ADV = LOW)
Note:
ADDRESS
ADDRESS
Page mode is a performance-enhancing extension to the legacy asynchronous READ
operation. In page-mode-capable products, an initial asynchronous read access is
performed, then adjacent addresses can be read quickly by simply changing the low-
order address. Addresses A[3:0] are used to determine the members of the 16-address
CellularRAM page. Any change in addresses A[4] or higher will initiate a new
time. Figure 7 shows the timing for a page mode access. Page mode takes advantage of
the fact that adjacent addresses can be read in a shorter period of time than random
addresses. WRITE operations do not include comparable page mode functionality.
During asynchronous page mode operation, the CLK input must be held static LOW or
HIGH. CE# must be driven HIGH upon completion of a page mode access. WAIT will be
driven while the device is enabled and its state should be ignored. Page mode is enabled
by setting RCR[7] to HIGH. ADV must be driven LOW during all page mode read
accesses.
LB#/UB#
LB#/UB#
DATA
DATA
WE#
OE#
WE#
CE#
ADV must remain LOW for page mode operation.
OE#
CE#
16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
t WC = WRITE Cycle Time
t RC = READ Cycle Time
ADDRESS VALID
ADDRESS VALID
<
t
11
CEM
DATA VALID
DATA VALID
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Bus Operating Modes
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AA access