ics9248-138 Integrated Device Technology, ics9248-138 Datasheet
ics9248-138
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ics9248-138 Summary of contents
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... Additional frequencies selectable through I ICS9248-138 Pin Configuration 1 48 VDDLAPIC IOAPIC 3 46 VDDLCPU 4 45 CPUCLK0 5 44 CPUCLK1 6 43 GNDLCPU 7 42 GNDSDR 8 41 SDRAM0 9 40 SDRAM1 10 39 ...
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... ICS9248-138 General Description The ICS9248-138 is the single chip clock solution for designs using the 810/810E and Solano style chipset. It provides all necessary clock signals for such a system. Spread spectrum may be enabled through I 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-138 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations ...
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... ± ICS9248-138 ...
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... ICS9248-138 Byte 1: SDRAM Control Register (1= enable disable ...
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... CONDITIONS = Inputs with no pull-up resistors = 0 V; Inputs with pull-up resistors = 0 pF; Select @ 66M = 0 pF; With input address to Vdd or GND = 3 3 target Freq ICS9248-138 +0 ...
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... ICS9248-138 Electrical Characteristics - CPU 70° 2.5 V +/-5 DDL PARAMETER SYMBOL 1 Output Impedance R DSP2B 1 Output Impedance R DSN2B Output High Voltage V OH2B Output Low Voltage V OL2B Output High Current I OH2B Output Low Current I OL2B 1 Rise Time t r2B 1 Fall Time t f2B 1 Duty Cycle ...
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... 2 =3.135 V OH @MIN OH@ MAX =0.4 V OL@ MIN OL@ MAX ICS9248-138 MIN TYP MAX UNITS 0.4 V -27 - 0.4 1.6 ns 0.4 1 250 ps 500 ps MIN TYP MAX UNITS ...
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... ICS9248-138 Electrical Characteristics - PCI 70° 3.3 V +/-5 PARAMETER SYMBOL 1 Output Impedance R DSP1 1 Output Impedance R DSN1 Output High Voltage V OH1 Output Low Voltage V OL1 Output High Current I OH1 Output Low Current I OL1 1 Rise Time Fall Time Duty Cycle ...
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... ACK ACK ACK ACK ACK 2 C component. It can read back the data stored in the latches for 2 C interface, the protocol is set to use only "Block-Writes" from the controller. The 9 ICS9248-138 2 C programming. How to Read: ICS (Slave/Receiver) Start Bit Address D3 (H) ACK Byte Count ...
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... ICS9248-138 Shared Pin Operation - Input/Output Pins The I/O pins designated by (input/output) on the ICS9248- 138 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of ...
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... As shown, the outputs Stop Low on the next falling edge after PD# goes low asynchronous input and metastable conditions may exist. This signal is synchronized inside this part. 4. The shaded sections on the VCO and the Crystal signals indicate an active clock. 5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz. 0342C—08/26/03 11 ICS9248-138 ...
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... ICS9248-138 INDEX INDEX AREA AREA 45° 45° .10 (.004) C .10 (.004) C Ordering Information ICS9248yF-138 Example: ICS XXXX PPP - T 0342C—08/26/03 c SYMBOL VARIATIONS Reference Doc.: JEDEC Publication 95, MO-118 ...