ics9248-128 Integrated Device Technology, ics9248-128 Datasheet
ics9248-128
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ics9248-128 Summary of contents
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... ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ICS9248-128 Pin Configuration 1 48 ...
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... ICS9248-128 Pin Descriptions P in number P in name 1 V DDR 1 ode 3,9,16,22, GND 27,33, 6,14 V DDP 1 CICLK _F P CICLK 0 1 13, 12, 11 CICLK (4:1) 15,28,29,31,32, S DRA M 12, 34,35,37,38 S DRA M (7:0) S DRA U_S TOP # S DRA CI-S TOP # 19 V DDS D/C ...
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... General Description The ICS9248-128 is the single chip clock solution for Desktop/Notebook designs using the SIS style chipset. It provides all necessary clock signals for such a system. Spread spectrum may be enabled through I This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-128 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations ...
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... ICS9248-128 Serial Configuration Command Bitmap Byte 0: Functionality and frequency select register (Default = ± ...
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... Notes: 1. Inactive means outputs are held LOW and are disabled from switching ICS9248-128 ...
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... ICS9248-128 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0 Ambient Operating Temperature . . . . . . . . . . . . . 0°C to +70°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied ...
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... CPU & SDRAM = 100 MHz 7 ICS9248-128 MIN TYP MAX UNITS 2.4 2.2 V 0.3 0.4 V - 175 ps 210 250 ps MIN TYP ...
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... ICS9248-128 Electrical Characteristics - PCICLK 70º 3.3 V +/- 5 PARAMETER SYMBOL Output High Voltage V OH1 Output Low Voltage V OL1 Output High Current I OH1 Output Low Current I OL1 1 Rise Time Fall Time Duty Cycle Skew t sk1 1 t Jitter, Cycle-to-cycle ...
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... V +/- (unless otherwise stated). DDL L CONDITIONS 2. ICS9248-128 MIN TYP MAX UNITS 2.4 2.6 V 0.3 0 600 1000 ps 400 500 ps ...
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... ICS9248-128 General I The information in this section assumes familiarity with I For more information, contact ICS for an I How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address D2 • ICS clock will acknowledge • Controller (host) sends a dummy command code • ...
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... CPU_STOP asychronous input to the clock synthesizer used to turn off the CPU clocks for low power operation. CPU_STOP# is synchronized by the ICS9248-128. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is 100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse ...
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... SDRAM_STOP sychronous input to the clock synthesizer used to turn off the CPU clocks for low power operation. SDRAM_STOP# is synchronized by the ICS9248-128. All other clocks will continue to run while the SDRAM clocks are disabled. The SDRAM clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse ...
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... PCI_STOP# Timing Diagram PCI_STOP synchronous input to the ICS9248-128 used to turn off the PCICLK (0:4) clocks for low power operation. PCI_STOP# is synchronized by the ICS9248-128 internally. The minimum that the PCICLK (0:4) clocks are enabled (PCI_STOP# high pulse least 10 PCICLK (0:4) clocks. PCICLK (0:4) clocks are stopped in a low state and started with a full high pulse width guaranteed ...
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... ICS9248-128 Shared Pin Operation - Input/Output Pins The I/O pins designated by (input/output) on the ICS9248- 128 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function ...
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... Routed Power = Ground Connection Key (component side copper) = Ground Plane Connection = Power Route Connection = Solder Pads = Clock Load 15 ICS9248-128 Ferrite C2 Bead 22µF/20V Tantalum VDD 2.5V Power Route Clock Load ...
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... ICS9248-128 Ordering Information ICS9248yF-128 Example: ICS XXXX PPP Pattern Number ( digit number for parts with ROM code patterns) Package Type F=SSOP Revision Designator Device Type (consists digit numbers) Prefix ICS Standard Device Third party brands and names are the property of their respective owners. ...