ics9248-135 Integrated Device Technology, ics9248-135 Datasheet
ics9248-135
Related parts for ics9248-135
ics9248-135 Summary of contents
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... ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ICS9248-135 1 48 REF1 ...
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... ICS9248-135 General Description The ICS9248-135 is the single chip clock solution for Desktop/Notebook designs using the SIS 540/630 style chipset. It provides all necessary clock signals for such a system. Spread spectrum may be enabled through I 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-135 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations ...
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... ACK ACK ACK ACK ACK 2 C component. It can read back the data stored in the latches for 2 C interface, the protocol is set to use only "Block-Writes" from the controller. The 3 ICS9248-135 2 C programming. How to Read: ICS (Slave/Receiver) Start Bit Address D3 (H) ACK Byte Count ...
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... ICS9248-135 Serial Configuration Command Bitmap Byte0: Functionality and Frequency Select Register (default = ...
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... Note: Don’t write into this register, writing into this register can cause malfunction 5 ICS9248-135 ...
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... ICS9248-135 Shared Pin Operation - Input/Output Pins The I/O pins designated by (input/output) serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function ...
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... CPU_STOP asychronous input to the clock synthesizer used to turn off the CPU clocks for low power operation. CPU_STOP# is synchronized by the ICS9248-135. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is 100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse ...
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... Crystal Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248-135 device shown, the outputs Stop Low on the next falling edge after PD# goes low asynchronous input and metastable conditions may exist. This signal is synchronized inside this part. ...
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... PCI_STOP# Timing Diagram PCI_STOP asynchronous input to the ICS9248-135 used to turn off the PCICLK clocks for low power operation. PCI_STOP# is synchronized by the ICS9248-135 internally. The minimum that the PCICLK clocks are enabled (PCI_STOP# high pulse least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a full high pulse width guaranteed ...
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... SDRAM_STOP asychronous input to the clock synthesizer used to stop SDRAM clocks for low power operation. SDRAM_STOP# is synchronized to complete it's current cycle, by the ICS9248-135. All other clocks will continue to run while the SDRAM clocks are disabled. The SDRAM clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse ...
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... 2.5 V +/-5% (unless otherwise stated) DDL CONDITIONS pF; Select @ 66.8 MHz pF; Select @ 100 MHz pF; Select @ 133 MHz ICS9248-135 +0.5 V MIN TYP MAX -0.3 0.8 SS 148 180 150 180 161 11 14.318 ...
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... ICS9248-135 Electrical Characteristics - CPU 70C VDDL = 3.3 V +/-5 PARAMETER SYMBOL 1 Output Impedance R DSP2A 1 Output Impedance R DSN2A Output High Voltage V OH1a Output Low Voltage V OL1a Output High Current I OH1a Output Low Current I OL1a 1 Rise Time t r1a 1 Fall Time t f1a 1 Duty Cycle ...
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... - ICS9248-135 MIN TYP MAX UNITS 2.4 3.3 V 0.17 0.4 V -62 - 1.62 2.2 ns 1. 200 500 ps -350 306 350 ps MIN ...
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... ICS9248-135 Electrical Characteristics - 48MHz, REF_0 70C 3.3 V +/-5 PARAMETER SYMBOL 1 Output Impedance R DSP1 1 Output Impedance R DSP1 Output High Voltage V OH2 Output Low Voltage V OL2 Output High Current I OH2 Output Low Current I OL2 1 Rise Time 48MHz Fall Time 48MHz ...
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... ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to 15 obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ICS9248-135 In Millimeters In Inches COMMON DIMENSIONS MIN ...