ics9248-135 Integrated Device Technology, ics9248-135 Datasheet - Page 2

• Manufacturer Part Number: ics9248-135
• Description: Frequency Generator & Integrated Buffers For Celeron
• Manufacturer: Integrated Device Technology

General Description
The ICS9248-135 is the single chip clock solution for Desktop/Notebook designs using the SIS 540/630 style chipset. It
provides all necessary clock signals for such a system.
Spread spectrum may be enabled through I
10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-135
employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature
variations.
Serial programming I
Pin Configuration
Third party brands and names are the property of their respective owners.
ICS9248-135
3, 10, 16, 22, 33,
PIN NUMBER
14, 13, 12, 11, 9
1, 6, 15, 19, 27,
38, 37, 35, 34,
32, 31, 29, 28
30, 36, 42
39, 44
41, 40
45, 43
17
18
20
21
23
24
25
26
46
47
48
2
4
5
7
8
SDRAM_STOP#
SDRAM_F (1:0)
CPUCLK (1:2)
SDRAM (7:0)
PCICLK (6:2)
CPU_STOP#
CPU2.5_3.3#
PIN NAME
PCI_STOP#
CPUCLK_F
VDDLCPU
PCICLK_F
24_48MHz
PCICLK1
2
SDATA
48MHz
C interface allows changing functions, stop clock programming and frequency selection.
SCLK
REF0
REF1
VDD
GND
PD#
FS3
FS1
FS2
FS0
X1
X2
TYPE
PWR
PWR
PWR
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
2
C programming. Spread spectrum typically reduces system EMI by 8dB to
3.3V Power supply for SDRAM output buffers, PCI output buffers, reference
output buffers and 48MHz output
14.318 MHz reference clock.
Frequency select pin.
Ground pin for 3V outputs.
Crystal input,nominally 14.318MHz.
Crystal output, nominally 14.318MHz.
Frequency select pin.
Free running PCICLK clock output. Not affected by PCI_STOP#
Frequency select pin.
PCI clock outputs.
PCI clock outputs.
Stops all SDRAMs besides the SDRAM_F clocks at logic 0 level, when input low
Asynchronous active low input pin used to power down the device into a low
power state. The internal clocks are disabled and the VCO and the crystal are
stopped. The latency of the power down will not be greater than 3ms.
Stops all CPUCLKs clocks at logic 0 level, when input low
Stops all PCICLKs clocks at logic 0 level, when input low
SDRAM clock outputs
Data input for I
Clock input of I
Voltage select 2.5V when high - 3.3V when low
Clock output for super I/O/USB default is 24MHz
Frequency select pin.
48MHz output clock
Free running SDRAM clock outputs. Not affected by SDRAM_STOP#
CPU clock outputs.
Free running CPUCLK clock output. Not affected by CPU_STOP#
Power pin for the CPUCLKs. 2.5V
14.318 MHz reference clock.
2
2
2
C serial input, 5V tolerant input
C input, 5V tolerant input
DESCRIPTION