ics673-01 Integrated Device Technology, ics673-01 Datasheet - Page 2

• Manufacturer Part Number: ics673-01
• Description: Pll Building Block
• Manufacturer: Integrated Device Technology

Pin Assignment
Pin Descriptions
IDT™ / ICS™ PLL BUILDING BLOCK
ICS673-01
PLL BUILDING BLOCK
Number
V C O IN
C H G P
Pin
10
11
12
13
14
15
16
F B IN
G N D
G N D
G N D
V D D
V D D
1
2
3
4
5
6
7
8
9
1 6 p in n a rro w (1 5 0 m il) S O IC
VCOIN
Name
REFIN
CHGP
CLK2
CLK1
FBIN
GND
GND
GND
VDD
VDD
CAP
SEL
Pin
1
2
3
4
5
6
7
8
OE
NC
PD
1 6
1 5
1 4
1 3
1 2
1 1
1 0
9
Output
Output
Output
Power
Power
Power
Power
Power
Type
Input
Input
Input
Input
Input
Input
Input
Pin
-
R E F IN
N C
C L K 1
C L K 2
P D
S E L
O E
C A P
Feedback clock input. Connect the feedback clock to this pin.
Triggered on falling edge.
Connect to +3.3 V or +5 V and to VDD on pin 3.
Connect to VDD on pin 2.
Connect to ground.
Connect to ground.
Connect to ground.
Charge pump output. Connect to VCOIN under normal operation.
Input to internal VCO.
Loop filter return.
Output enable. Active when high. Tri-states both outputs when low.
Internal weak pull-up resistor.
Select pin for VCO predivide to feedback divider per table above.
Internal weak pull-up resistor.
Power down. Turns off entire chip when pin is low. Outputs stop low.
Internal weak pull-up resistor.
Clock output 2. Low skew divide by two version of CLK1.
Clock output 1.
No connect. Nothing is connected internally to this pin.
Reference input. Connect reference clock to this pin. Triggered on
falling edge.
2
VCO Predivide Select Table
Pin Description
0 = connect pin directly to ground
1 = connect pin directly to VDD
SEL
0
1
VCO Predivide
ICS673-01
PLL BUILDING BLOCK
4
1
REV Q 071906