ics673-01 Integrated Device Technology, ics673-01 Datasheet - Page 6

• Manufacturer Part Number: ics673-01
• Description: Pll Building Block
• Manufacturer: Integrated Device Technology

The CLK output frequency may be up to 2x the maximum
Output Clock Frequency listed in the AC Electrical
Characteristics above when the device is in an unlocked
condition. Make sure that the external divider can operate
up to this frequency.
Figure 3. Example Configuration -- Generating a 20 MHz clock from a 200 kHz reference.
IDT™ / ICS™ PLL BUILDING BLOCK
ICS673-01
PLL BUILDING BLOCK
R
R
2
3
CHGP
Figure 2. Using an External Comparator
VCOIN
to Reset the VCO
200 kHz
0.01 F
R
S
C
P
R
4
+
C
-
CAP
S
+3.3 or 5 V
SEL
REFIN
FBIN
PD
200 kHz
OE PD
such as ICS674-01
Digital Divider
VDD
100
ICS673-01
CHGP
6
VCOIN
Explanation of Operation
The ICS673-01 is a PLL building block circuit that includes
an integrated VCO with a wide operating range. The device
uses external PLL loop filter components which through
proper configuration allow for low input clock reference
frequencies, such as a 15.7 kHz Hsync input.
The phase/frequency detector compares the falling edges of
the clocks inputted to FBIN and REFIN. It then generates an
error signal to the charge pump, which produces a charge
proportional to this error. The external loop filter integrates
this charge, producing a voltage that then controls the
frequency of the VCO. This process continues until the
edges of FBIN are aligned with the edges of the REFIN
clock, at which point the output frequency will be locked to
the input frequency.
R
GND
S
C
P
C
S
CLK2
CLK1
CAP
20 MHz
40 MHz
ICS673-01
PLL BUILDING BLOCK
REV Q 071906