ics673-01 Integrated Device Technology, ics673-01 Datasheet - Page 7

• Manufacturer Part Number: ics673-01
• Description: Pll Building Block
• Manufacturer: Integrated Device Technology

Determining the Loop Filter Values
The loop filter components consist of C
Calculating these values is best illustrated by an example.
Using the example in Figure 1, we can synthesize 20 MHz
from a 200 kHz input.
The phase locked loop may be approximately described by
the following equations:
As a general rule, the bandwidth should be at least 20 times
less than the reference frequency, i.e.,
In this example, using the above equation, bandwidth
should be less than or equal to 10 kHz. By setting the
bandwith to 10kHz and using the first equation, R
determined since all other variables are known. In the
example of Figure 1, N = 200, comprising the divide by 2 on
the chip (VCO post divider) and the external divide by 100.
Therefore, the bandwidth equation becomes:
and R
Choosing a damping factor of 0.7 (a minimal damping factor
than can be used to ensure fast lock time), damping factor
equation becomes:
IDT™ / ICS™ PLL BUILDING BLOCK
ICS673-01
PLL BUILDING BLOCK
0,000
Bandwidth
Damping factor,
where:
BW REFIN
S
0.7
= 26 k
K
I
N = Total feedback divide from VCO,
C
R
cp
=
O
S
S
=
= Charge pump current (A)
= VCO gain (Hz/V)
= Loop filter capacitor (Farads)
= Loop filter resistor (Ohms)
25 000
--------------- -
including the internal VCO post divider
R
------------------------------------------------------------------
,
NBW
S
2
190
=
20
=
190
---------------------------------------------------------------------
R
----- -
2
R
------------------------------- -
2
S
S
10
10
K
---------------------------------- -
6
2 N
K
200
O
6
O
2.5
I
200
I
2.5
CP
N
CP
S
, C
10
P
C
10
, and R
–
S
–
6
S
can be
S
C
.
S
7
and C
The capacitor C
charge pump and should be approximately 1/20th the size
of C
Therefore, C
To summarize, the loop filter components are:
Output Clock Alignment to REFIN
When choosing either CLK1 or CLK2 to drive the feedback
divider, ICS recommends that CLK2 be used so that the
falling edges of CLK2 and REFIN, and the rising edge of
CLK1, are all synchronized. If CLK1 is used for feedback,
CLK2 may be either a rising or falling edge when compared
to REFIN. See diagrams below.
S
, i.e.,
C
C
C
R
S
P
S
P
S
= 1.32 nF (1.2 nF is the nearest standard value).
= 1.2 nf
= 56 pf
= 26 k
C
P
S
REFIN
REFIN
CLK2
CLK2
CLK1
= 60 pF (56 pF nearest standard value).
CLK1
P
20
is used to damp transients from the
CLK2 Feedback
CLK1 Feedback
ICS673-01
PLL BUILDING BLOCK
REV Q 071906