ics673-01 Integrated Device Technology, ics673-01 Datasheet - Page 4

• Manufacturer Part Number: ics673-01
• Description: Pll Building Block
• Manufacturer: Integrated Device Technology

AC Electrical Characteristics
External Components
The ICS673-01 requires a minimum number of external
components for proper operation. A decoupling capacitor of
0.01 F should be connected between VDD and GND as
close to the ICS673-01 as possible. A series termination
resistor of 33 may be used at the clock output.
Special considerations must be made in choosing loop
components C
http://www.icst.com/products/telecom/loopfiltercap.htm
IDT™ / ICS™ PLL BUILDING BLOCK
ICS673-01
PLL BUILDING BLOCK
VDD = 3.3 V ±5%, Ambient Temperature -40 to +85 C, C
VDD = 5.0 V ±10%, Ambient Temperature -40 to +85 C, C
Note 1: Minimum input frequency is limited by loop filter design. 1 kHz is a practical minimum limit.
Output Clock Frequency
(from pin CLK)
Input Clock Frequency
(into pins REFIN or FBIN)
Output Rise Time
Output Fall Time
Output Clock Duty Cycle
Jitter, Absolute peak-to-peak
VCO Gain
Charge Pump Current
Output Clock Frequency
(from pin CLK)
Input Clock Frequency
(into pins REFIN or FBIN)
Output Rise Time
Output Fall Time
Output Clock Duty Cycle
Jitter, Absolute peak-to-peak
VCO Gain
Charge Pump Current
S
and C
Parameter
Parameter
P
. These can be found online at
Symbol
Symbol
f
f
f
f
t
t
t
t
t
t
CLK
REF
K
CLK
REF
K
I
I
OR
DC
OR
DC
OF
OF
t
t
cp
cp
J
J
O
O
SEL = 1
SEL = 0
0.8 to 2.0 V
2.0 to 0.8 V
At VDD/2
SEL = 1
SEL = 0
0.8 to 2.0 V
2.0 to 0.8 V
At VDD/2
Conditions
Conditions
4
Avoiding PLL Lockup
In some applications, the ICS673-01 can “lock up” at the
maximum VCO frequency. This is usually caused by power
supply glitches or a very slow power supply ramp. This
situation also occurs if the external divider starts to fail at
high input frequencies. The usual failure mode of a divider
circuit is that the output of the divider begins to miss clock
edges. The phase detector interprets this as a too low
output frequency and increases the VCO frequency. The
LOAD
LOAD
at CLK = 15 pF, unless stated otherwise.
at CLK = 15 pF, unless stated otherwise.
Note 1
Note 1
Min.
Min.
0.25
0.25
40
45
1
1
Typ. Max. Units
Typ. Max. Units
0.75
250
190
150
190
1.2
2.5
0.5
0.5
2.4
50
50
ICS673-01
PLL BUILDING BLOCK
100
120
1.5
25
60
30
55
8
2
8
1
1
MHz/V
MHz/V
MHz
MHz
MHz
MHz
MHz
MHz
ns
ns
ps
ns
ns
ps
%
%
A
A
REV Q 071906