ics1893cy-10 Integrated Device Technology, ics1893cy-10 Datasheet - Page 49

• Manufacturer Part Number: ics1893cy-10
• Description: 3.3-v 10base-t/100base-tx Integrated Phyceiver
• Manufacturer: Integrated Device Technology

6.5.3 10Base-T Operation: Clock Recovery
6.5.4 10Base-T Operation: Idle
6.5.5 10Base-T Operation: Link Monitor
ICS1893CY-10 Rev 1/07
The ICS1893CY-10 recovers its receive clock from the Manchester-encoded data stream obtained from its
Twisted-Pair Receiver using a phase-locked loop (PLL). The ICS1893CY-10 then uses this recovered clock
for synchronizing data transmission between itself and the MAC/repeater. Receive-clock PLL acquisitions
begin with reception of the MAC Frame Preamble and continue as long as the ICS1893CY-10 is receiving
data.
An ICS1893CY-10 transmits Normal Link Pulses (that is, 10Base-T Idles) on its MDI in the absence of data
(that is, when the MAC/repeater is not requiring it to transmit any data). During this time the link is Idle, and the
ICS1893CY-10 periodically transmits link pulses at a rate of one link pulse every 16 ms in compliance with the
ISO/IEC 8802-3 standard. In 10Base-T mode, the ICS1893CY-10 continues transmitting link pulses even
while receiving data. This situation does not generate a Collision Detect signal (COL) because link pulses
indicate an idle state for a link.
When an ICS1893CY-10 is in 10Base-T mode, its Link Monitor Function observes the data received by the
10Base-T Twisted-Pair Receiver to determine the link status. The results of this continual monitoring are
stored in the Link Status bit. The Station Management entity (STA) can access the Link Status bit in either
the Status Register (bit 1.2) or the QuickPoll Detailed Status Register (bit 17.0).
When the Link Status bit is:
•
•
The ICS1893CY-10 Link Status bit is a latching low (LL) bit. (For more information on latching high and
latching low bits, see
The criteria used by the Link Monitor Function to declare a link either valid (that is, ‘established’ or ‘up’) or
invalid (that is, ‘failed’ or ‘down’) depends upon these factors: the present state of the link, whether its
Smart Squelch function is enabled, and the incoming data.
When the 10Base-T link is:
•
•
Zero, either a valid link is not established or the link is momentarily dropped since either the last read of
the Link Status bit or the last reset of the ICS1893CY-10.
One, a valid link is established.
Invalid, and the Smart Squelch function is:
Valid, and the Smart Squelch function is:
– Disabled (bit 18.0 is logic 1), the Link Monitor Function must detect at least one of the following
– Enabled (bit 18.0 is logic 0), the Link Monitor Function must detect at least one of the following
– Disabled (bit 18.0 is logic 1), the Link Monitor Function continues to report its link as valid as long as
ICS1893CY-10 - Release
events before transitioning its link from the invalid state to the valid state:
events before transitioning its link from the invalid state to the valid state:
it continues to detect any of the following:
• More than seven, ISO/IEC-defined, Normal Link Pulses (NLPs)
• Any valid data
• More than seven, ISO/IEC-defined, Normal Link Pulses (NLPs)
• Any valid data followed by a valid IDL
• ISO/IEC-defined, Normal Link Pulses (NLPs)
• Any valid data
Section 7.1.4.1, “Latching High Bits”
Copyright © 2007, Integrated Device Technology, Inc.
All rights reserved.
49
and
Section 7.1.4.2, “Latching Low
Chapter 6 Functional Blocks
Bits”.)