m29w400b-100za6tr STMicroelectronics, m29w400b-100za6tr Datasheet - Page 27

• Manufacturer Part Number: m29w400b-100za6tr
• Description: 64 Mbit 8mb X8 Or 4mb X16, Multiple Bank, Boot Block 3v Supply Flash Memory
• Manufacturer: STMicroelectronics

M29DW640F
4.2.5
4.2.6
Octuple Byte Program
This is used to write eight adjacent Bytes, in x8 mode, in parallel. The addresses of the eight
Bytes must differ only in A1, A0 and DQ15A-1.
Nine bus write cycles are necessary to issue the command.
1.
2.
3.
4.
5.
6.
7.
8.
9.
Only one bank can be programmed at any one time. The other bank must be in Read mode
or Erase Suspend.
After programming has started, Bus Read operations in the Bank being programmed output
the Status Register content, while Bus Read operations to the other Bank output the
contents of the memory array.
Programming can be suspended and then resumed by issuing a Program Suspend
command and a Program Resume command, respectively. (See
Suspend command
After the program operation has completed the memory will return to the Read mode, unless
an error has occurred. When an error occurs Bus Read operations to the Bank where the
command was issued will continue to output the Status Register. A Read/Reset command
must be issued to reset the error condition and return to Read mode.
Note that the Fast Program commands cannot change a bit set at ’0’ back to ’1’. One of the
Erase Commands must be used to set all the bits in a block or in the whole memory from ’0’
to ’1’.
Typical Program times are given in
Endurance
Unlock Bypass command
The Unlock Bypass command is used in conjunction with the Unlock Bypass Program
command to program the memory faster than with the standard program commands. When
the cycle time to the device is long, considerable time saving can be made by using these
commands. Three Bus Write operations are required to issue the Unlock Bypass command.
Once the Unlock Bypass command has been issued the bank enters Unlock Bypass mode.
The Unlock Bypass Program command can then be issued to program addresses within the
bank, or the Unlock Bypass Reset command can be issued to return the bank to Read
mode. In Unlock Bypass mode the memory can be read as if in Read mode.
The first bus cycle sets up the command.
The second bus cycle latches the Address and the Data of the first Byte to be written.
The third bus cycle latches the Address and the Data of the second Byte to be written.
The fourth bus cycle latches the Address and the Data of the third Byte to be written.
The fifth bus cycle latches the Address and the Data of the fourth Byte to be written.
The sixth bus cycle latches the Address and the Data of the fifth Byte to be written.
The seventh bus cycle latches the Address and the Data of the sixth Byte to be written.
The eighth bus cycle latches the Address and the Data of the seventh Byte to be
written.
The ninth bus cycle latches the Address and the Data of the eighth Byte to be written
and starts the Program/Erase Controller.
cycles.
and
Section 4.1.9: Program Resume
command
Table 8: Program, Erase times and Program, Erase
command)
Section 4.1.8: Program
Command interface
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