pc87311a National Semiconductor Corporation, pc87311a Datasheet - Page 51

• Manufacturer Part Number: pc87311a
• Description: Pc87311a/pc87312 Superi/otm Ii/iii Floppy Disk Controller With Dual Uarts, Parallel Port, And Ide Interface
• Manufacturer: National Semiconductor Corporation

6 0 Serial Ports
6 2 3 Programmable Baud Rate Generator
The PC87311A contains two independently programmable
Baud rate Generators The 24 MHz crystal oscillator fre-
quency input is divided by 13 resulting in a frequency of
1 8462 MHz This is sent to each Baud rate Generator and
divided by the divisor of the associated UART The output
frequency of the Baud rate Generator (BOUT1 2) is 16
the baud rate
The output of each Baud rate Generator drives the transmit-
ter and receiver sections of the associated serial channel
Two 8-bit latches per channel store the divisor in a 16-bit
binary format These Divisor Latches must be loaded during
initialization to ensure proper operation of the Baud rate
Generator Upon loading either of the Divisor Latches a
16-bit Baud Counter is loaded Table 6-4 provides decimal
divisors to use with crystal frequencies of 24 MHz The os-
cillator input to the chip should always be 24 MHz to ensure
that the Floppy Disk Controller timing is accurate and that
the UART divisors are compatible with existing software
Using a divisor of zero is not recommended
Note The percent error for all baud rates except where indicated otherwise
is 0 2%
6 2 4 Line Status Register
This 8-bit register provides status information to the CPU
concerning the data transfer Table 6-2 shows the contents
of the Line Status Register Details on each bit follow
Bit 0
Baud Rate
divisor
50
75
110
134 5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
57600
115200
This bit is the receiver Data Ready (DR) indicator Bit
0 is set to logic 1 whenever a complete incoming
character has been received and transferred into the
Receiver Buffer Register Bit 0 is reset to a logic 0 by
reading the data in the Receiver Buffer Register
TABLE 6-4 PC87311A UART Divisors
24 MHz Input Divided to 1 8432 MHz
Baud Rates and Clock Frequencies
e
(frequency input) (baud rate
Decimal Divisor
for 16 x Clock
(Continued)
2304
1536
1047
857
768
384
192
96
64
58
48
32
24
16
12
6
3
2
1
Percent
c
Error
0 1
0 4
0 5
16)
c
51
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
This bit is the Overrun Error (OE) indicator Bit 1 indi-
cates that data in the Receiver Buffer Register was
not read by the CPU before the next character was
transferred into the Receiver Buffer Register there-
by destroying the previous character The OE indica-
tor is set to a logic 1 upon detection of an overrun
condition and reset whenever the CPU reads the
contents of the Line Status Register
This bit is the Parity Error (PE) indicator Bit 2 indi-
cates that the received data character does not have
the correct even or odd parity as selected by the
even-parity select bit The PE bit is set to a logic 1
upon detection of a parity error and is reset to a logic
0 whenever the CPU reads the contents of the Line
Status Register
This bit is the Framing Error (FE) indicator Bit 3 indi-
cates that the received character did not have a val-
id Stop bit Bit 3 is set to a logic 1 whenever the Stop
bit following the last data bit or parity bit is a logic 0
(Spacing level) The FE indicator is reset whenever
the CPU reads the contents of the Line Status Reg-
ister The UART will try to resynchronize after a
framing error To do this it assumes that the framing
error was due to the next start bit so it samples this
‘‘start’’ bit twice and then takes in the bits following it
as the rest of the frame
This bit is the Break Interrupt (BI) indicator Bit 4 is
set to a logic 1 whenever the received data input is
held in the Spacing (logic 0) state for longer than a
full word transmission time (that is the total time of
Start bit
indicator is reset whenever the CPU reads the con-
tents of the Line Status Register Restarting after a
break is received requires the SIN pin to be logical 1
for at least
Note Bits 1 through 4 are the error conditions that produce a
This bit is the Transmitter Holding Register Empty
(THRE) indicator Bit 5 indicates that the UART is
ready to accept a new character for transmission In
addition this bit causes the UART to issue an inter-
rupt to the CPU when the Transmiter Holding Regis-
ter Empty Interrupt enable is set high The THRE bit
is set to a logic 1 when a character is transferred
from the Transmitter Holding Register into the
Transmitter Shift Register The bit is reset to logic 0
whenever the CPU loads the Transmitter Holding
Register
This bit changes its function depending on whether
the device is operating in the XT or AT mode When
operating in the AT mode this bit is the Transmitter
Empty (TEMT) indicator Bit 6 is set to a logic 1
whenever the Transmitter Holding Register (THR)
and the Transmitter Shift Register (TSR) are both
empty It is reset to a logic 0 whenever either the
THR or TSR contains a data character When oper-
ating in the XT mode this bit is set whenever the
Transmitter Shift Register is empty It is cleared
whenever a byte is loaded into the Transmit Shift
Register
Receiver Line Status interrupt whenever any of the corre-
sponding conditions are detected and the interrupt is en-
abled
a
data bits
bit time
a
Parity
a
Stop bits) The BI