pc87311a National Semiconductor Corporation, pc87311a Datasheet - Page 59

• Manufacturer Part Number: pc87311a
• Description: Pc87311a/pc87312 Superi/otm Ii/iii Floppy Disk Controller With Dual Uarts, Parallel Port, And Ide Interface
• Manufacturer: National Semiconductor Corporation

6 0 Serial Ports
6 3 9 MODEM Status Register (MSR)
This register provides the current state of the control lines
from the MODEM (or peripheral device) to the CPU In addi-
tion to this current-state information four bits of the
MODEM Status Register provide change information These
bits are set to a logic 1 whenever a control input from the
MODEM changes state They are reset to logic 0 whenever
the CPU reads the MODEM Status Register Table 6-7
shows the contents of the MSR Details on each bit follow
Bit 0 This bit is the Delta Clear to Send (DCTS) indicator
Bit 1 This bit is the Delta Data Set Ready (DDSR) indica-
Bit 2 This bit is the Trailing Edge of Ring Indicator (TERI)
Bit 3 This bit is the Delta Data Carrier Detect (DDCD) indi-
Bit 4 This bit is the complement of the Clear to Send (CTS)
Bit 5 This bit is the complement of the Data Set Ready
Bit 6 This bit is the complement of the Ring Indicator (RI)
Bit 7 This bit is the complement of the Data Carrier Detect
6 3 10 Scratchpad Register (SCR)
This 8-bit Read Write Register does not control the UART
in any way It is intended as a scratchpad register to be used
by the programmer to hold data temporarily
7 0 Parallel Port
7 1 INTRODUCTION
This parallel interface is designed to provide all of the sig-
nals and registers needed to communicate through a stan-
dard parallel printer port as found in the IBM PC XT AT
PS 2 and Centronics systems The address decoding of the
registers utilizing A0 and A1 is shown in Table 7-1 Table 7-3
shows the Reset states of Parallel port registers and pin
signals All bits in these registers are located in the same
positions and have the same functions as the registers of
the systems listed above These registers are shown in Sec-
tions 7-2 – 7-4
A1
0
0
1
1
TABLE 7-1 Parallel Interface Register Addresses
Bit 0 indicates that the CTS input to the chip has
changed state since the last time it was read by the
CPU
tor Bit 1 indicates that the DSR input to the chip has
changed state since the last time it was read by the
CPU
detector Bit 2 indicates that the RI input to the chip
has changed from a low to a high state
cator Bit 3 indicates that the DCD input to the chip
has changed state
Note Whenever bit 0 1 2 or 3 is set to logic 1 a MODEM Status
input If bit 4 (loopback) of the MCR is set to a 1 this
bit is equivalent to RTS in the MCR
(DSR) input If bit 4 of the MCR is set to a 1 this bit is
equivalent to DTR in the MCR
input If bit 4 of the MCR is set to a 1 this bit is
equivalent to OUT1 in the MCR
(DCD) input If bit 4 of the MCR is set to a 1 this bit is
equivalent to IRQ ENABLE in the MCR
A0
0
1
0
1
Interrupt is generated
Address
0
1
2
3
(Continued)
Data
Status
Control
TRI-STATE
Register
Read Write
Read
Read Write
Access
59
A special back voltage protection circuit is implemented
against damage that might be caused when the printer is
powered but the PC87311A or PC87312 device is not
There are two modes of operation (see Table 7-2) Compati-
ble (PTR7
mode is the same as the basic operating mode for the
PC-AT and the Extended mode is identical to the PS 2 Ex-
tended mode There are 3 features which distinguish Ex-
tended mode from Compatible Mode
1 Port direction is controlled by the CTR5 bit
2 The interrupt is latched on the rising edge of ACK rather
3 The STR2 bit monitors the interrupt status
In Compatible mode the direction of data flow is controlled
at reset time by the PDIR pin (PDIR
and PDIR
mode causes the data to be presented on pins PD0 – 7 The
read operation causes the Data Register to present the last
data written to it by the CPU
In the Extended Mode a write operation to the Data Regis-
ter causes the data to be latched If the Data Port Direction
bit (CTR5) is 0 the latched data is presented to the pins if it
is 1 the data is only latched When Data Port Direction bit
(CTR5) is 0 a read operation from the Data Register allows
the CPU to read the last data it wrote to the port In the
Extended Mode with the Data Port Direction bit set to 1
(read) a read from this register causes the port to present
the data on pins PD0 – PD7
PTR7
than following ACK continuously
0
0
0
0
1
1
1
1
TABLE 7-2 Data Register Read and Write Modes
Port Function
Compatible
Extended
TABLE 7-3 Parallel Port Mode of Operation
PDIR
e
e
0
1
0
1
X
X
X
X
0) and Extended (PTR7
1
e
CTR5
input direction) A write operation in this
X
X
X
X
0
1
0
1
RD
1
1
0
0
1
1
0
0
PTR7
WR
0
0
1
1
0
0
1
1
0
1
e
e
0
Data Written to
PD0 – PD7
Data Written is
Latched
Data Read from
the Output Latch
Data Read from
PD0 – PD7
Data Written to
PD0 – PD7
Data Written is
Latched
Data Read from
the Output Latch
Data Read from
PD0 – PD7
1) The Compatible
e
output direction
Result
POE
1
0