pc87311a National Semiconductor Corporation, pc87311a Datasheet - Page 9

• Manufacturer Part Number: pc87311a
• Description: Pc87311a/pc87312 Superi/otm Ii/iii Floppy Disk Controller With Dual Uarts, Parallel Port, And Ide Interface
• Manufacturer: National Semiconductor Corporation

Symbol
IDENT
INDEX
INIT
IOCS16
IRQ3 4
IRQ5
IRQ6
IRQ7
MR
1 0 Pin Description
1 100
Pin
54
47
80
59
98
97
96
2
I O
O
O
O
O
O
I
I
I
I
Identity During chip reset the IDENT and MFM pins are sampled to determine the mode of operation
according to the following table
AT Mode The DMA enable bit in the DOR is valid TC is active high Status Registers A and B are
disabled (TRI-STATE)
Model 30 Mode The DMA enable bit in the DOR is valid TC is active high Status Registers A and B
are enabled
PS 2 Mode The DMA enable bit in the DOR is a don’t care and the DRQ and IRQ6 signals will always
be enabled TC is active low Status Registers A and B are enabled
After chip reset the state of IDENT determines the polarity of the DENSEL output
When IDENT is a logic ‘‘1’’ DENSEL is active high for the 500 kbs 1 Mbs data rates
When IDENT is a logic ‘‘0’’ DENSEL is active low for the 500 kbs 1 Mbs data rates
(See Mode command for further explanation of DENSEL )
Index This input signals the beginning of a FDD track
Initialize When this signal is low it causes the printer to be initialized This pin will be in a TRI-STATE
condition 10 ns after a zero is loaded into the corresponding Control Register bit The system should pull
this pin high using a 4 7 kX resistor
I O Chip Select 16-Bit This input will be driven by the peripheral device when it can accommodate a
16-bit access
Interrupt 3 and 4 These are active high interrupts associated with the serial ports IRQ3 presents the
signal if the serial channel has been designated as COM2 or COM4 IRQ4 presents the signal if the serial
port is designated as COM1 or COM3 The appropriate interrupt goes active whenever it is enabled via
IER the associated Interrupt Enable bit (Modem Control Register bit 3 MCR3) and any of the following
conditions are active Receiver Error Receive Data available Transmitter Holding Register Empty or a
Modem Status Flag is set The interrupt is reset low (inactive) after the appropriate interrupt service
routine is executed after being disabled via the IER or after a Master Reset Either interrupt can be
disabled putting them into TRI-STATE by setting the MCR3 bit low
Interrupt 5 Active high output that indicates a parallel port interrupt When enabled this bit follows the
ACK signal input When bit 4 in the parallel port Control Register is set and the parallel port address is
designated as shown in Table 2-5 this interrupt is enabled When it is not enabled or when operating in
the XT mode this signal is TRI-STATE
Interrupt 6 Active high output to signal the completion of the execution phase for certain FDC
commands Also used to signal when a data transfer is ready during a Non-DMA operation When in
PC-AT or Model 30 mode this signal is enabled by bit D3 of the DOR When in PS 2 mode IRQ6 is
always enabled and bit D3 of the DOR is reserved
Interrupt 7 Active high output that indicates a parallel port interrupt When enabled this bit follows the
ACK signal input When bit 4 in the parallel port Control Register is set and the parallel port address is
designated as shown in Table 2-5 this interrupt is enabled When it is not enabled this signal is
TRI-STATE
Master Reset Active high input that resets the controller to the idle state and resets all disk interface
outputs to their inactive states The DOR DSR CCR Mode command Configure command and Lock
command parameters are cleared to their default values The Specify command parameters are not
affected The Configuration Registers are set to their selected default values
IDENT
(Continued)
1
1
0
0
1 or NC
1 or NC
MFM
0
0
Model 30 Mode
PC-AT Mode
PS 2 Mode
MODE
Illegal
9
Function