w83194r-81 Winbond Electronics Corp America, w83194r-81 Datasheet
w83194r-81
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w83194r-81 Summary of contents
Page 1
... W83194R-81 provides the 0.25%, 0.5% center type spread spectrum to reduce EMI. The W83194R-81 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply. High drive PCI and SDRAM CLOCK outputs typically provide greater than 1 V /ns slew rate into 30 pF loads. CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20 pF loads as maintaining 50¡ ...
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... Reg. 1 Vdd 2 3 Vss Xin 4 Xout Vss Vss Vss W83194R-81 PRELIMINARY 48MHz SIO REF(0:2) 3 IOAPIC CPUCLK(0:2) 3 SDRAM(0:12) 13 PCICLK(0:4) 5 PCICLK_F Vddq2 48 IOAPIC 47 46 REF1/ *SD_SEL# 45 Vss REF2/CPU3.3_2.5# 44 CPUCLK0 43 Vddq2b 42 41 CPUCLK1 40 CPUCLK 2 Vss ...
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... SDRAM clock outputs which have the same frequency as CPU clocks. 7 I/O Latched input for FS1 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks. Free running PCI clock during normal operation W83194R-81 PRELIMINARY FUNCTION FUNCTION Publication Release Date: Dec. 1998 Revision 0.20 ...
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... SIO=14.318. If logic 1, SIO=24MHz for super I/O. 26 I/O Internal 250k Latched input for FS0 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks. 48MHz output for USB during normal operation W83194R-81 PRELIMINARY FUNCTION FUNCTION 2 C 2-wire control interface 2 C 2-wire control interface FUNCTION pull-up. ...
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... W83194R-81 PRELIMINARY FUNCTION PCI REF (MHz) (MHz) (MHz) IOAPIC 33.35 14.318 30 14.318 31.7 14.318 33.4 14.318 30 14.318 37.3 14.318 31 14.318 33.3 14.318 33.4 14.318 30 14.318 33.32 14.318 31.7 14.318 33.4 14.318 37.3 14.318 31 14.318 33.3 14 ...
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... CPU 3.3#_2.5 BUFFER SELECTION CPU 3.3#_2.5 ( Pin 44 ) Input Level 1 0 CPU Operate at VDD = 2.5V VDD = 3.3V Publication Release Date: Dec. 1998 - 6 - W83194R-81 PRELIMINARY Revision 0.20 ...
Page 7
... The W83194R-81 may be disabled in the low state according to the following table in order to reduce power consumption. All clocks are stopped in the low state, but maintain a valid high period on transitions from running to stop ...
Page 8
... All proceeding bytes must be sent to change one of the control bytes. The 2-wire control interface allows each clock output individually enabled or disabled. W83194R-81 initializes with default register settings, and then it optional to use the 2-wire control interface. The SDATA signal only changes when the SDCLK signal is low, and is stable when SDCLK is high during normal data transfer ...
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... W83194R-81 PRELIMINARY Bit 6:4 and Bit2 PCI REF (MHz) (MHz) IOAPIC 33.35 14.318 30 14.318 31.7 14.318 33.4 14.318 30 14.318 37.3 14.318 31 14.318 33.3 14.318 33.4 14.318 30 14.318 33.32 14.318 31 ...
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... PCICLK2 (Active / Inactive) PCICLK1 (Active / Inactive) PCICLK0 (Active / Inactive) Description SDRAM7 (Active / Inactive) SDRAM6 (Active / Inactive) SDRAM5 (Active / Inactive) SDRAM4 (Active / Inactive) SDRAM3 (Active / Inactive) SDRAM2 (Active / Inactive) SDRAM1 (Active / Inactive) SDRAM0 (Active / Inactive W83194R-81 PRELIMINARY Publication Release Date: Dec. 1998 Revision 0.20 ...
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... Reserved IOAPIC (Active / Inactive) Latched SD_SEL REF2 (Active / Inactive) REF1 (Active / Inactive) REF0 (Active / Inactive) Description Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip W83194R-81 PRELIMINARY Publication Release Date: Dec. 1998 Revision 0.20 ...
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... CCJ 500 500 J 0.4 1.6 t TLH t THL V 1.5 over V 2.1 RBE - 12 - W83194R-81 PRELIMINARY Rating - 0 7 150 125 + Units Test Conditions % Measured at 1. Load Measured at 1. Load Measured at 1. KHz Load on CPU and PCI ...
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... Ioz 10 I dd3 I dd2 CPUS3 CPUS2 I PD3 - 13 - W83194R-81 PRELIMINARY = + Units Test Conditions All outputs V dc All outputs using 3.3V power CPU = 66.6 MHz PCI = 33.3 Mhz with load mA Same as above mA ...
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... Max -27 OH(min) -27 OH(max) I OL(min OL(max) 0.4 RF(min) 1.6 RF(max) Min Typ Max -29 OL(min) 28 OL(max) 0.4 RF(min) 1.8 RF(max W83194R-81 PRELIMINARY Units Test Conditions mA Vout = 1 Vout = 2.0V mA Vout = 1 Vout = 0 Load Load Units Test Conditions mA Vout = 1 Vout = 2.7V mA Vout = 1 Vout = 0 ...
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... Min Typ Max -46 OL(min) 53 OL(max) 0.5 RF(min) 1.3 RF(max) Min Typ Max -33 -33 30 OL(min) 38 OL(max) 0.5 RF(min) 2.0 RF(max W83194R-81 PRELIMINARY Units Test Conditions mA Vout = 1 Vout = 3.135V mA Vout = 1. Vout = 0 Load Load Units Test Conditions mA Vout = 1.65V mA Vout = 3.135V mA Vout = 1. Vout = 0 ...
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... PCI clocks locks on latency “ is less than 2 CPU clocks and 1 2 locks on latency “ is less than 1 PCI clocks and locks off - 16 - W83194R-81 PRELIMINARY ctive low ” input pin used to stop the Publication Release Date: Dec. 1998 ...
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... W83194R-81 12.0 HOW TO READ THE TOP MARKING W83194R-81 28051234 814GBB 1st line: Winbond logo and the type number: W83194R-81 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 814 814: packages made in '98, week 14 G: assembly house ID ...
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... Winbond Electronics (H.K.) Ltd. Rm. 803, World Trade Square, Tower II 123 Hoi Bun Rd., Kwun Tong Kowloon, Hong Kong TEL: 852-27516023-7 FAX: 852-27552064 Publication Release Date: Dec. 1998 - 18 - W83194R-81 PRELIMINARY Winbond Electronics (North America) Corp. 2730 Orchard Parkway San Jose, CA 95134 U.S.A. TEL: 1-408-9436666 FAX: 1-408-9436668 ...