lmk03000c National Semiconductor Corporation, lmk03000c Datasheet
lmk03000c
Related parts for lmk03000c
lmk03000c Summary of contents
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... RMS ( MHz). When configured as a jitter cleaner, the LMK03000C/LMK03001C features jitter performance of 400 fs RMS (12 kHz - 20 MHz) and the LMK03000C/LMK03001C 800 fs RMS (12 kHz - 20 MHz). The clock conditioners come in a 48-pin LLP package and are footprint compatible with other clocking devices in the same family ...
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Functional Block Diagram Connection Diagram www.national.com 48-Pin LLP Package 2 20211401 20211402 ...
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Pin Descriptions Pin # 13, 16, 19, 22, 26, Vcc1, Vcc2, Vcc3, Vcc4, Vcc5, Vcc6, Vcc7, Vcc8, 30, 31, 33, 37, 40, 43, 46 Vcc9, Vcc10, Vcc11, Vcc12, Vcc13, Vcc14 34, ...
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Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Parameter Power Supply Voltage Input Voltage Storage Temperature Range Lead Temperature (solder 4 s) Junction Temperature Recommended Operating Conditions ...
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... PLL_CP_GAIN = 32x PLL_CP_GAIN = 1x PLL_CP_GAIN = 32x VCO LMK03000/LMK03000C LMK03001/LMK03001C After programming R15 for lock, no changes to output configuration are permitted to guarantee continuous lock. (Note 8) LMK03000/LMK03000C; T LMK03001/LMK03001C; T LMK03000/LMK03000C LMK03001/LMK03001C LMK03000/LMK03001 12 kHz to 20 MHz bandwidth LMK03000C/LMK03001C 12 kHz to 20 MHz bandwidth 10 kHz Offset LMK03000C 100 kHz Offset ...
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Symbol Parameter Clock Distribution Section (Note 10) - LVDS Clock Outputs (CLKout0 to CLKout2) Jitter Additive RMS Jitter (Note 10) ADD t CLKoutX to CLKoutY (Note 11) SKEW V Differential Output Voltage OD Change in magnitude of V ΔV OD ...
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Symbol Parameter t Data to Clock Set Up Time CS t Data to Clock Hold Time CH t Clock Pulse Width High CWH t Clock Pulse Width Low CWL t Clock to Enable Set Up Time ES t Enable to ...
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Charge Pump Current Specification Definitions I1 = Charge Pump Sink Current Charge Pump Sink Current Charge Pump Sink Current Charge Pump Source Current Charge ...
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... Two VCO frequency plans are available for each performance grade. The LMK03000 and LMK03000C include a 1.24 GHz VCO. The LMK03001 and LMK03001C include a 1.52 GHz VCO. The VCO output is optionally accessible on the Fout port ...
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CLKout OUTPUT STATES Each clock output may be individually enabled with the CLKoutX_EN bits. Each individual output enable control bit is gated with the Global Output Enable input pin (GOE) and the Global Output Enable bit (EN_CLKout_Global). All clock ...
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... General Programming Information The LMK03000/LMK03000C/LMK03001/LMK03001C devices are programmed using several 32-bit registers which control the device's operation. The registers consist of a data field and an address field. The last 4 register bits, ADDR[3:0] form the address field. The remaining 28 bits form the data field DATA[27:0]. ...
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CLKout0_EN CLKout1_EN CLKout2_EN CLKout3_EN CLKout4_EN CLKout5_EN CLKout6_EN CLKout7_EN RESET Register www.national.com 12 ...
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DIV4 POWERDOWN EN_CLKout_Global EN_Fout Register 13 www.national.com ...
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REGISTER Registers R0 through R7 control the eight clock outputs. Register R0 controls CLKout0, Register R1 controls CLKout1, and so on. There is one additional bit in register R0 called RESET. Aside from this, the functions ...
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CLKoutX_DIV[7:0] -- Clock Output Dividers These bits control the clock output divider value. In order for these dividers to be active, the respective CLKoutX_MUX (See 2.3.2) bit must be set to either "Divided" or "Divided and Delayed" mode. After ...
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REGISTER R11 This register only has one bit and only needs to be programmed in the case that the phase detector frequency is greater than 20 MHz and digital lock detect is used. Otherwise automatically defaulted to ...
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VCO_R4_LF[2:0] -- Value for Internal Loop Filter Resistor R4 These bits control the R4 resistor value in the internal loop filter. The recommended setting for VCO_R4_LF[2: for optimum phase noise and jitter. VCO_R4_LF[2: 2.5.4 ...
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PLL_MUX[3:0] -- Multiplexer Control for LD Pin These bits set the output mode of the LD pin. The table below lists several different modes. PLL_MUX[3: ...
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Register R15 Programming R15 also activates the frequency calibration routine. 2.7.1 PLL_N[17:0] -- PLL N Divider These bits program the divide value for the PLL N Divider. The PLL N Divider follows the VCO Divider and precedes the PLL ...
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Application Information 3.1 SYSTEM LEVEL DIAGRAM The following shows the LMK300xx in a typical application. In this setup the clock may be multiplied, reconditioned, and redis- tributed. The first and second pole of the loop filter are external. The ...
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LOOP FILTER The internal charge pump is directly connected to the integrated loop filter components. The first and second pole of the loop filter are externally attached as shown in Figure 2. When the loop filter is designed, it ...
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... V) 2 3.6 THERMAL MANAGEMENT Power consumption of the LMK03000/LMK03000C/LMK03001/LMK03001C devices can be high enough to require attention to thermal management. For reliability and performance reasons the die temperature should be limited to a maximum of 125 °C. That (ambient temperature) plus device power consumption times θ is estimate, T ...
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FIGURE 3. Recommended Land and Via Pattern To minimize junction temperature it is recommended that a simple heat sink be built into the PCB (if the ground plane layer is not exposed). This is done by including a copper area ...
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... Package Marking LMK03000ISQ K03000 I LMK03000ISQX K03000 I LMK03001ISQ K03001 I LMK03001ISQX K03001 I LMK03000CISQ K03000CI LMK03000CISQX K03000CI LMK03001CISQ K03001CI LMK03001CISQX K03001CI www.national.com inches (millimeters) unless otherwise noted Leadless Leadframe Package (Bottom View) 48 Pin LLP (SQA48A) Package Packing VCO Version 250 Unit Tape and Reel 1 ...
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Notes 25 www.national.com ...
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