lmk03000c National Semiconductor Corporation, lmk03000c Datasheet - Page 9

• Manufacturer Part Number: lmk03000c
• Description: Precision Clock Conditioner With Integrated Vco
• Manufacturer: National Semiconductor Corporation

1.0 Functional Description
The LMK03000/LMK03000C/LMK03001/LMK03001C preci-
sion clock conditioners combine the functions of jitter clean-
ing/reconditioning, multiplication, and distribution of a refer-
ence clock. The devices integrate a Voltage Controlled
Oscillator (VCO), a high performance Integer-N Phase
Locked Loop (PLL), a partially integrated loop filter, three
LVDS, and five LVPECL clock output distribution blocks.
When configured as a clock generator with a wide loop band-
width, a high phase detector frequency, and a low noise clock
source the LMK03000C/LMK03001C features jitter perfor-
mance of 200 fs RMS (10 Hz - 20 MHz). When configured as
a jitter cleaner, the LMK03000C/LMK03001C features jitter
performance of 400 fs RMS (12 kHz - 20 MHz) and the
LMK03000C/LMK03001C 800 fs RMS (12 kHz - 20 MHz).
The devices include internal 3rd and 4th order poles to sim-
plify loop filter design and improve spurious performance. The
1st and 2nd order poles are off-chip to provide flexibility for
the design of various loop filter bandwidths.
Two VCO frequency plans are available for each performance
grade. The LMK03000 and LMK03000C include a 1.24 GHz
VCO. The LMK03001 and LMK03001C include a 1.52 GHz
VCO. The VCO output is optionally accessible on the Fout
port. Internally, the VCO output goes through an VCO Divider
to feed the various clock distribution blocks.
Each clock distribution block includes a programmable di-
vider, a phase synchronization circuit, a programmable delay,
a clock output mux, and an LVDS or LVPECL output buffer.
This allows multiple integer-related and phase-adjusted
copies of the reference to be distributed to eight system com-
ponents.
The clock conditioners come in a 48-pin LLP package and are
footprint compatible with other clocking devices in the same
family.
1.1 BIAS PIN
To properly use the device, bypass Bias (pin 36) with a low
leakage 1 µF capacitor connected to Vcc. This is important
for low noise performance.
1.2 LDO BYPASS
To properly use the device, bypass LDObyp1 (pin 9) with a
10 µF capacitor and LDObyp2 (pin 10) with a 0.1 µF capacitor.
1.3 OSCILLATOR INPUT PORT (OSCin, OSCin*)
The purpose of OSCin is to provide the PLL with a reference
signal. The OSCin port must be AC coupled, refer to the Sys-
tem Level Diagram in the Application Information section. The
OSCin port may be driven single endedly by AC grounding
OSCin* with a 0.1 µF capacitor.
1.4 LOW NOISE, FULLY INTEGRATED VCO
The LMK03000/LMK03000C/LMK03001/LMK03001C de-
vices contain a fully integrated VCO. In order for proper
operation the VCO uses a frequency calibration algorithm.
The frequency calibration algorithm is activated any time that
9
the R15 register is programmed. Once R15 is programmed
the temperature may not drift more than the maximum allow-
able drift for continuous lock, ΔT
guaranteed to stay in lock.
For the frequency calibration algorithm to work properly OS-
Cin must be driven by a valid signal when R15 is programmed.
1.5 CLKout DELAYS
Each individual clock output includes a delay adjustment.
Clock output delay registers (CLKoutX_DLY) support a 150
ps step size and range from 0 to 2250 ps of total delay.
1.6 LVDS/LVPECL OUTPUTS
Each LVDS or LVPECL output may be disabled individually
by programming the CLKoutX_EN bits. All the outputs may
be disabled simultaneously by pulling the GOE pin low or
programming EN_CLKout_Global to 0.
1.7 GLOBAL CLOCK OUTPUT SYNCHRONIZATION
The SYNC* pin synchronizes the clock outputs. When the
SYNC* pin is held in a logic low state, the outputs are also
held in a logic low state. When the SYNC* pin goes high, the
clock outputs are activated and will transition to a high state
simultaneously.
The SYNC* pin must be held low for greater than one clock
cycle of the output of the VCO Divider, also known as the
distribution path. Once this low event has been registered, the
outputs will not reflect the low state for four more cycles. Sim-
ilarly once the SYNC* pin becomes high, the outputs will not
simultaneously transition high until four more distribution path
clock cycles have passed. See the timing diagram below for
further detail. In the timing diagram below the clocks are pro-
grammed as CLKout0_MUX = Bypassed, CLKout1_MUX =
Divided, CLKout1_DIV = 2, CLKout2_MUX = Divided, and
CLKout2_DIV = 4.
SYNC* Timing Diagram
The SYNC* pin provides an internal pull-up resistor as shown
on the functional block diagram. If the SYNC* pin is not ter-
minated externally the clock outputs will operate normally. If
the SYNC* function is not used, clock output synchronization
is not guaranteed.
CL
, or else the VCO is not
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