lmk03000c National Semiconductor Corporation, lmk03000c Datasheet - Page 19

• Manufacturer Part Number: lmk03000c
• Description: Precision Clock Conditioner With Integrated Vco
• Manufacturer: National Semiconductor Corporation

2.7 Register R15
Programming R15 also activates the frequency calibration routine.
2.7.1 PLL_N[17:0] -- PLL N Divider
These bits program the divide value for the PLL N Divider. The PLL N Divider follows the VCO Divider and precedes the PLL phase
detector. Since the VCO Divider is also in the feedback path from the VCO to the PLL Phase Detector, the total N divide value,
N
f
divide values for PLL_N[17:0] except for 0.
2.7.2 VCO_DIV[3:0] -- VCO Divider
These bits program the divide value for the VCO Divider. The VCO Divider follows the VCO output and precedes the clock distri-
bution blocks. Since the VCO Divider is in the feedback path from the VCO to the PLL phase detector the VCO Divider contributes
to the total N divide value, N
Divider) for more information on setting the VCO frequency.
2.7.3 PLL_CP_GAIN[1:0] -- PLL Charge Pump Gain
These bits set the charge pump gain of the PLL.
VCO
Total
0
0
0
1
.
.
= f
, is also influenced by the VCO Divider value. N
OSCin
0
0
0
1
.
.
0
0
0
0
0
0
0
0
1
1
1
.
× PLL N Divider × VCO Divider / PLL R Divider. Since the PLL N divider is a pure binary counter there are no illegal
0
0
0
1
.
.
0
0
0
1
.
.
PLL_CP_GAIN[1:0]
0
0
0
1
.
.
Total
0
0
0
1
.
.
0
0
0
0
1
1
1
1
0
0
1
0
1
2
3
.
. N
Total
VCO_DIV[3:0]
0
0
0
1
.
.
= PLL N Divider × VCO Divider. The VCO Divider can not be bypassed. See 2.7.1 (PLL N
0
0
0
1
.
.
PLL_N[17:0]
0
0
1
1
.
.
0
0
0
1
.
.
0
0
1
1
0
0
1
1
0
0
1
.
Total
0
0
1
1
= PLL N Divider × VCO Divider. The VCO frequency is calculated as,
.
.
19
0
0
1
1
.
.
0
0
1
1
.
.
0
1
0
1
0
1
0
1
0
1
1
.
0
0
1
1
.
.
0
0
1
1
.
.
0
0
0
1
Charge Pump Gain
.
.
1x (default)
0
0
0
1
.
.
16x
32x
4x
0
1
0
1
VCO Divider Value
.
.
2 (default)
PLL N Divider Value
Invalid
Invalid
Invalid
Invalid
...
3
4
5
6
7
8
760 (default)
262143
Invalid
...
...
1
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