pck953 NXP Semiconductors, pck953 Datasheet - Page 5

• Manufacturer Part Number: pck953
• Description: 50-125 Mhz Pecl Input/9 Cmos Output 3.3 V Pll Clock Driver
• Manufacturer: NXP Semiconductors

Philips Semiconductors
APPLICATION INFORMATION
Power supply filtering
The PCK953 is a mixed analog/digital product and as such it
exhibits some sensitivities that would not necessarily be seen on a
fully digital product. Analog circuitry is naturally susceptible to
random noise, especially if this noise is seen on the power supply
pins. The PCK953 provides separate power supplies for the output
buffers (V
purpose of this design technique is to try to isolate the HIGH
switching noise digital outputs from the relatively sensitive internal
analog phase-locked loop. In a controlled environment such as an
evaluation board, this level of isolation is sufficient. However, in a
digital system environment where it is more difficult to minimize
noise on the power supplies, a second level of isolation may be
required. The simplest form of isolation is a power supply filter on
the V
Figure 1 illustrates a typical power supply filter scheme. The
PCK953 is most susceptible to noise with spectral content in the
1 kHz to 1 MHz range. Therefore, the filter should be designed to
target this range. The key parameter that needs to be met in the
final filter design is the DC voltage drop that will be seen between
the V
datasheet, the I
pin) is typically 15 mA (20 mA maximum), assuming that a minimum
of 3.0 V must be maintained on the V
drop can be tolerated when a 3.3 V V
shown in Figure 1 must have a resistance of 10-15 Ω to meet the
voltage drop criteria. The RC filter pictured will provide a broadband
filter with approximately 100:1 attenuation for noise whose spectral
content is above 20 kHz. As the noise frequency crosses the series
resonant point of an individual capacitor, its overall impedance
begins to look inductive, and thus increases with increasing
frequency. The parallel capacitor combination shown ensures that a
low impedance path to ground exists for frequencies well above the
bandwidth of the PLL. It is recommended that the user start with an
8-10 Ω resistor to avoid potential V
move to the higher value resistors when a higher level of attenuation
is shown to be needed.
Although the PCK953 has several design features to minimize the
susceptibility to power supply noise (isolated power and grounds
and fully differential PLL) there still may be applications in which
overall performance is being degraded due to system power supply
noise. The power supply filter schemes discussed in this section
should be adequate to eliminate power supply noise related
problems in most designs.
2003 Jul 31
20-125 MHz PECL input / 9 CMOS output
3.3 V PLL clock driver
CCA
CC
supply and the V
CCO
pin for the PCK953.
PCK953
) and the phase-locked loop (V
VCCA
PLL_V
Figure 1. Power supply filter
current (the current sourced though the V
V
CC
CC
CCA
0.01 µF
pin of the PCK953. From the
R
S
CC
= 5-15 Ω
CCA
CC
drop problems, and only
22 µF
supply is used. The resistor
pin, very little DC voltage
0.01 µF
3.3 V
CCA
) of the device. The
SW00626
CCA
5
Driving transmission lines
The PCK953 clock driver was designed to drive high speed signals
in a terminated transmission line environment. To provide the
optimum flexibility to the user, the output drivers were designed to
exhibit the lowest impedance possible. With an output impedance of
less than 20 Ω, the drivers can drive either parallel or series
terminated transmission lines.
In most high performance clock networks, point-to-point distribution
of signals is the method of choice. In a point-to-point scheme either
series terminated or parallel terminated transmission lines can be
used. The parallel technique terminates the signal at the end of the
line with a 50 Ω resistance to V
high level of DC current, and thus only a single terminated line can
be driven by each output of the PCK953 clock driver. For the series
terminated case, however, there is no DC current draw, thus the
outputs can drive multiple series terminated lines. Figure 2 illustrates
an output driving a single series terminated line versus two series
terminated lines in parallel. When taken to its extreme, the fanout of
the PCK953 clock driver is effectively doubled due to its capability to
drive multiple lines.
The waveform plots of Figure 3 show the simulation results of an
output driving a single line versus two lines. In both cases, the drive
capability of the PCK953 output buffers is more than sufficient to
drive 50 Ω transmission lines on the incident edge. Note from the
delay measurements in the simulations, a delta of only 43 ps exists
between the two differently loaded outputs. This suggests that the
dual line driving need not be used exclusively to maintain the tight
output-to-output skew of the PCK953. The output waveform in
Figure 3 shows a step in the waveform; this step is caused by the
impedance mismatch seen looking into the driver. The parallel
combination of the 43 Ω series resistor plus the output impedance
does not match the parallel combination of the line impedances. The
voltage wave launched down the two lines will equal:
VL = VS (Z
Z
R
R
VL = 3.0 (25 / (18 + 14 + 25) = 3.0 (25 / 57) = 1.31 V
O
S
O
= 50 Ω ø 50 Ω
= 36 Ω ø 36 Ω
= 14 Ω
IN
IN
Figure 2. Single versus dual transmission lines
PCK953
PCK953
OUTPUT
OUTPUT
O
BUFFER
BUFFER
14 Ω
14 Ω
/ (R
S
+ R
O
+ Z
R
R
R
S
S
S
O
CC
= 36 Ω
= 36 Ω
= 36 Ω
))
/2. This technique draws a fairly
Z
Z
Z
O
O
O
= 50 Ω
= 50 Ω
= 50 Ω
PCK953
SW00627
Product data
OutA
OutB0
OutB1