adf4106-ep Analog Devices, Inc., adf4106-ep Datasheet - Page 4

• Manufacturer Part Number: adf4106-ep
• Description: Pll Frequency Synthesizer Adf4106-ep
• Manufacturer: Analog Devices, Inc.

ADF4106-EP
Parameter
NOISE CHARACTERISTICS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
TIMING CHARACTERISITICS
AV
unless otherwise noted.
Table 2.
Parameter
t
t
t
t
t
t
1
Timing Diagram
1
2
3
4
5
6
Operating temperature range is −55°C to +125°C.
This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that
is less than this value.
AV
AC coupling ensures AV
Guaranteed by design. Sample tested to ensure compliance.
T
T
T
T
value) and 10 log F
frequency offset, f, is given by PN = P
the synthesizer (f
Operating temperature range (B Version) is –40°C to +85°C.
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider
The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, f
The phase noise is measured with the EVAL-ADF4106-EB1 evaluation board and the Agilent E4440A spectrum analyzer. The spectrum analyzer provides the REF
f
f
f
A
A
A
A
REFIN
REFIN
REFIN
Normalized Phase Noise Floor (PN
Normalized 1/f Noise (PN
Phase Noise Performance
Spurious Signals
= 25°C; AV
= 25°C; AV
= 25°C; AV
= 25°C; AV
DD
DD
900 MHz
5800 MHz
5800 MHz
900 MHz
5800 MHz
5800 MHz
= DV
= 10 MHz; f
= 10 MHz; f
= 10 MHz; f
= DV
DD
= 3 V.
DD
DD
DD
DD
DD
13
13
= DV
= DV
= DV
= DV
= 3 V ± 10%, AV
PFD
PFD
PFD
14
15
14
15
REFOUT
PFD
= 200 kHz; offset frequency = 1 kHz; f
= 200 kHz; offset frequency = 1 kHz; f
= 1 MHz; offset frequency = 1 kHz; f
DD
DD
DD
DD
. PN
= 10 MHz @ 0 dBm).
= 3 V; P = 16; RF
= 3 V; P = 16; RF
= 3 V; P = 32; RF
= 3.3 V; R = 16383; A = 63; B = 891; P = 32; RF
DD
SYNTH
/2 bias.
= PN
CLOCK
1_f
12
DATA
)
TOT
11
LE
LE
DD
1_f
− 10 log F
IN
IN
IN
+ 10log(10 kHz/f) + 20log(f
≤ V
= 900 MHz.
= 2.0 GHz.
= 6.0 GHz.
Limit
10
10
25
25
10
20
DB23 (MSB)
SYNTH
P
≤ 5.5 V, AGND = DGND = CPGND = 0 V, R
PFD
)
1
10
(B Version)
− 20 log N.
RF
RF
RF
= 5800 MHz; N = 5800; loop B/W = 100 kHz.
t
1
= 900 MHz; N = 4500; loop B/W = 20 kHz.
= 5800 MHz; N = 29,000; loop B/W = 20 kHz.
DB22
B Version
−223
−122
−92.5
−76.5
−83.5
−90/−92
−65/−70
−70/−75
t
RF
2
IN
/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL.
= 6.0 GHz.
Figure 2. Timing Diagram
Rev. A | Page 4 of 12
1
DB2
Unit
ns min
ns min
ns min
ns min
ns min
ns min
Unit
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc typ
dBc typ
dBc typ
t
3
t
DB1 (CONTROL
4
BIT C2)
Test Conditions/Comments
DATA to CLOCK Setup Time
DATA to CLOCK Hold Time
CLOCK High Duration
CLOCK Low Duration
CLOCK to LE Setup Time
LE Pulse Width
SET
Test Conditions/Comments
PLL loop BW = 500 kHz
Measured at 10 kHz offset; normalized to 1 GHz
VCO output
1 kHz offset and 200 kHz PFD frequency
1 kHz offset and 200 kHz PFD frequency
1 kHz offset and 1 MHz PFD frequency
200 kHz/400 kHz and 200 kHz PFD frequency
200 kHz/400 kHz and 200 kHz PFD frequency
1 MHz/2 MHz and 1 MHz PFD frequency
= 5.1 kΩ, dBm referred to 50 Ω, T
(CONTROL BIT C1)
t
5
DB0 (LSB)
t
6
A
= T
MAX
RF
, and at a
to T
IN
MIN
for
,