adf4106-ep Analog Devices, Inc., adf4106-ep Datasheet - Page 6

• Manufacturer Part Number: adf4106-ep
• Description: Pll Frequency Synthesizer Adf4106-ep
• Manufacturer: Analog Devices, Inc.

ADF4106-EP
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Table 4. Pin Function Descriptions
Pin No.
TSSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin No.
LFCSP
19
20
1
2, 3
4
5
6, 7
8
9, 10
11
12
13
14
15
16, 17
18
CPGND
Figure 3. 16-Lead TSSOP Pin Configuration
NOTES:
1. TRANSISTOR COUNT 6425 (CMOS),
AGND
RF
RF
REF
AV
303 (BIPOLAR).
R
SET
IN
IN
CP
DD
IN
B
A
Mnemonic
R
CP
CPGND
AGND
RF
RF
AV
REF
DGND
CE
CLK
DATA
LE
MUXOUT
DV
V
EP
1
2
3
4
5
6
7
8
SET
P
IN
IN
ADF4106-EP
DD
DD
IN
B
A
(Not to Scale)
TOP VIEW
Description
Connecting a resistor between this pin and CPGND sets the maximum charge pump output current. The
nominal voltage potential at the R
So, with R
Charge Pump Output. When enabled, this provides ±I
the external VCO.
Charge Pump Ground. This is the ground return path for the charge pump.
Analog Ground. This is the ground return path of the prescaler.
Complementary Input to the RF Prescaler. This point must be decoupled to the ground plane with a
small bypass capacitor, typically 100 pF.
Input to the RF Prescaler. This small signal input is ac-coupled to the external VCO.
Analog Power Supply. This can range from 2.7 V to 3.3 V. Decoupling capacitors to the analog ground
plane should be placed as close as possible to this pin. AV
Reference Input. This is a CMOS input with a nominal threshold of V
resistance of 100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator or it can be ac-coupled.
Digital Ground.
Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into
three-state mode. Taking the pin high powers up the device, depending on the status of the power-
down bit, F2.
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched
into the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input
is a high impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of
the four latches with the latch being selected using the control bits.
This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference frequency to
be accessed externally.
Digital Power Supply. This can range from 2.7 V to 3.3 V. Decoupling capacitors to the digital ground
plane should be placed as close as possible to this pin. DV
Charge Pump Power Supply. This should be greater than or equal to V
can be set to 5.5 V and used to drive a VCO with a tuning range of up to 5 V.
Exposed Pad. The exposed pad must be connected to AGND.
16
15
14
13
12
11
10
9
I
CP
V
DV
MUXOUT
LE
DATA
CLK
CE
DGND
P
MAX
DD
SET
=
= 5.1 kΩ, I
R
25
SET
5 .
CP MAX
Rev. A | Page 6 of 12
= 5 mA.
SET
pin is 0.66 V. The relationship between I
CPGND 1
Figure 4. 20-Lead LFCSP Pin Configuration
CP
NOTES
1. TRANSISTOR COUNT 6425 (CMOS),
2. THE EXPOSED PAD MUST BE
AGND 2
AGND 3
RF
RF
303 (BIPOLAR).
CONNECTED TO AGND.
to the external loop filter, which in turn drives
IN
IN
DD
DD
B 4
A 5
must be the same value as DV
must be the same value as AV
ADF4106-EP
(Not to Scale)
TOP VIEW
PIN 1
INDICATOR
DD
/2 and a dc equivalent input
DD
. In systems where V
CP
15 MUXOUT
14 LE
13 DATA
12 CLK
11 CE
and R
SET
is
DD
DD
DD
.
.
is 3 V, it