pll102-108 PhaseLink Corp., pll102-108 Datasheet - Page 9

• Manufacturer Part Number: pll102-108
• Description: Programmable Zero Delay Clock Driver
• Manufacturer: PhaseLink Corp.

3. Recommended Operating Conditions
4. Timing requirements
5. Switching Characteristics
47745 Fremont Blvd., Fremont, California 94538 TEL [phone] FAX [phone]
Output supply voltage
Analog Supply voltage
High level input voltage
Low level input voltage
Operating free-air temperature
Low to high level propagation
delay time
High to low level propagation
delay time
Jitter (peak to peak)
Jitter (cycle to cycle)
Phase error
Output to output skew
Pulse skew
Duty Cycle
Rise time, Fall time
SYMBOL
PARAMETERS
F
D
T
CLK
PARAMETERS
IN
S
Stabilization time after power up
SYMBOL
t
(phase error)
Input clock duty cycle
T
Input clock frequency
T
T
T
T
T
cyc-cyc
t
oskew
pskew
D
r,
PLH
PHL
PARAMETERS
p-p
T
t
f
SYMBOL
Programmable DDR Zero Delay Clock Driver
All differential input and output
terminals are terminated with
A
V
V
V
T
CC
CC
IH
IL
A
CLK_INT to any output
CLK_INT to any output
100/133/200/266MHz
100/133/200/266MHz
101MHz to 266MHz
Load = 120
66MHz to 100MHz
CONDITIONS
120
66MHz
66MHz
16pF
16pF
0.7 x V
MIN.
2.3
2.3
0
CC
MIN.
66
40
MIN.
-150
49.5
650
49
TYP.
2.5
2.5
PLL102-108
MAX.
TYP.
266
800
0.1
60
0
0
0.3 x V
MAX.
2.7
2.7
70
Rev 03/29/02 Page 9
CC
MAX.
50.5
120
110
150
100
100
950
75
65
51
UNITS
MHz
UNITS
ms
%
UNITS
V
V
V
V
C
ns
ps
ps
ps
ps
%